TEMA 7. Tecnología y fabricación de CIs. G. Fabricación de dispositivos: Etapa CMOS

Transcripción

1 TEMA 7 Tecnología y fabricación de CIs G. Fabricación de dispositivos: Etapa CMOS 1

2 II. Fabricación de una etapa inversora CMOS Inversor (NOT) 2

3 II. Fabricación de una etapa inversora CMOS The following discussion will concentrate on the wellestablished CMOS fabrication technology, which requires that both n-channel (nmos) and p-channel (pmos) transistors be built on the same chip substrate. To accommodate both nmos and pmos devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well CMOS fabrication technology, the nmos transistor is created in the p-type substrate, and the pmos transistor is created in the n-well, which is built-in into the p-type substrate. Oxide Isolation G G -V SS S D D S +V DD p + n + n + p + p + n + n-well n-mosfet p-mosfet 3

4 II. Fabricación de una etapa inversora CMOS The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown. Starts with the creation of the n-well regions for pmos transistors, by impurity implantation into the substrate. A thick oxide is grown surrounding the nmos and pmos regions. The thin gate oxide is grown on the surface by thermal oxidation. Polysilicon of the gate is deposited. Creation of n+ and p+ regions (source, drain and channel-stop implants) Together with a self-aligning of the gate. Finally the metallization is created (creation of metal interconnects). Oxide Isolation Metallization G G -V SS S D D S +V DD p + n + n + p + p + n + n-well n-mosfet p-mosfet 4

5 II. Fabricación de una etapa inversora CMOS 1. Substrate. 5

6 2. The first step is to form the SiO2 layer(0.5-1um thick) by thermal oxidation. Etapa 1: crecimiento de la capa de óxido nativo. The oxidation temperature is generally in the range of degree C, and the typical gas flow rate is about 1cm/s. The method of producing an oxide layer consists of heating a silicon wafer in an oxidizing atmosphere. The wafer boat is slowly inserted into a fused silica tube wrapped in an electrical heating mantle. The temperature of the wafers gradually rises as Oxygen gas blowing through the tube passes over the surface of wafers. And oxygen molecules can actually diffuse through the oxide layer to reach the underlying silicon. There, oxygen and silicon react, and the layer of oxide gradually grows thicker. 6

7 3. Following oxidation, several drops of positive Photoresist are dropped on the wafer. Etapa 2: Apertura de la ventana del transistor P-MOS Primer proceso fotolitográfico Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer is spun at about 3000rpm to be uniformly spread out. After the spinning step, the wafer is given a pre-exposure baking ( degree C) to remove the solvent from the PR film and improve adhesion to the substrate. 7

8 4. Proceso de implantación iónica y difusión del pozo N. Etapa 3: formación del pozo N del transistor P-MOS After the oxide etch, ion implantation deposits a controlled dose of phosphorus through the etched window. A prolonged high-temperature drive creates a deep lightly doped N-type region called, N-Well. 8

9 5. Crecimiento de la capa de óxido de campo. Etapa 4: Óxido de campo Idéntica a la primera etapa. 9

10 6. Define the active area (Drain and Source regions) by photolithography. Etapa 5: Definición de S y D Segundo proceso fotolitográfico 10

11 7. Crecimiento de una delgada capa de oxido nativo: OXIDO DE PUERTA. Etapa 6: Crecimiento de una delgada capa de óxido de puerta 11

12 8. Creación de los contactos de puerta: Deposición de Poli-Silicio. Etapa 7: Contactos de puerta de Poly-Si Polysilicon Deposition: A patterned poly layer is produced by first depositing polsilicon across the wafer. The wafer is then coated with photoresist, patterned, and etched to selectively remove the polysilicon. 12

13 8. Litografía del Poly-Si de los contactos de puerta Etapa 8: Litografía de Poly-Si de puerta Tercer proceso fotolitográfico Polysilicon Deposition: A patterned poly layer is produced by first depositing polsilicon across the wafer. The wafer is then coated with photoresist, patterned, and etched to selectively remove the polysilicon. 13

14 9. Creación de Litografía para Implantación de Arsénico de regiones n+. Etapa 9: Litografía para definir las regiones n+ Cuarto proceso fotolitográfico The arsenic implant begins with the application of photoresist to the wafer, followed by patterning using the NSD mask. 14

15 10. Creación de fuente y drenador tipo n+ mediante Implantación de Arsénico. Etapa 10: Implantación iónica de las regiones n+ Shalllow, heavily doped N-type regions are then formed by implanting arsenic through the exposed gate oxide. Proceso de AUTOALINEADO: The polysilicon gate blocks this implant from the regions directly underneath the gate and therefore minimizes the gate/source and gate/drain overlap capacitances. Once the implant has been completed, the photoresist residue is stripped from the wafer. 15

16 11. Proceso litográfico para definir las regiones p+ de fuente y drenador Etapa 11: Litografía para definir las regiones p+ Quinto proceso fotolitográfico The boron implant begins with the application of a second photoresist layer patterned using the PSD mask. 16

17 12. Crear las regiones p+ de fuente y drenador mediante implante de boro. Etapa 12: Implantación de las regiones p+ A shallow, heavily doped P-type region is formed by implanting boron through the exposed gate oxide. As with the NSD implant, the PSD implant self-aligns to the polysilicon and the PMOS transistors also exhibit minimal overlap capacitance. Following the PSD implant, photoresist is again stripped from the wafer. 17

18 13. Crecimiento de óxido de pasivación: Protección del dispositivo. Etapa 13: Oxidación 18

19 14. Proceso fotolitográfico para la creación de las vías de metalizaciones de fuente y drenador. Etapa 14: Litografía para definir vias de metalizaciones de S y D Sexto proceso fotolitográfico 19

20 15. Deposición de las Interconexiones de aluminio. Etapa 14: Deposición de aluminio A thin film of refractory metal sputtered over the wafer precedes a much thicker layer of copper-doped aluminum. The metallized wafer is coated with photoresist and patterned, using the metal mask. A suitable etchant then removes unwanted metal to form the interconnection pattern. 20

21 16. Finalización. Etapa 15: Litografía para dividir metalizaciones de G, S y D Septimo proceso fotolitográfico Tras el último paso litográfico se termina el proceso de fabricación. Se muestra la conexiones de tierra, polarización, la unión de los terminales de puerta (terminal Vi de la etpa inversora) y el terminal de salida V0. Se muestra también la vista superior (layout del circuito). 21