INAOE (National Institute for Astrophysics, Optics and Electronics)

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1 CURRICULUM VITAE 1. NAME: Miguel Octavio Arias Estrada 2. BIRTH DATE AND PLACE: May 8th, 1968, Mexico City, D.F. 3. ADDRESS Work: INAOE, Computer Science Apdo. Postal 51 y Puebla, Pue. MEXICO Tel +52 (222) ext 8316 Cel +521 (222) Fax +52 (222) ariasmo@inaoep.mx ariasmo@ieee.org Skype: arias.m 4. LANGUAGES: English, French and Spanish (all written and spoken fluently). 5. CURRENT WORK DETAILS DEPARTMENT: Computer Science EMPLOYER: INAOE (National Institute for Astrophysics, Optics and Electronics) DATE OF ENGAGEMENT: 15/August/98 as full time Researcher CURRENT POSITION: Titular Researcher B (since July 1 st, 2007) SNI: SNI I, since July 2002, #20965 CVU (Conacyt CV System number): X_marias20965 RFC (Mexico Tax Payer Number): AIEM G4 CURP (Mexico ID Number): AIEM680508HDFRSG04 Mexican Social Security Number: Short Biography Miguel Arias-Estrada obtained his B.Eng. in Communications and Electronics, and his M.Eng in Digital Sytems at the FIMEE (University of Guanajuato) in Salamanca, Gto. in 1990 and 1992 respectively. In 1998, he obtained his Ph.D. degree at the Computer Vision and Systems Laboratory of Université Laval (Quebec city, Canada). He was a professor-researcher at the Computer and Systems Laboratory at Laval University where he worked on the development of a Smart Vision Camera. Since 1998 he is with the Computer Science department of INAOE (National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico) where he continues his research on FPGA architectures for computer vision. His interests are Computer Vision, FPGA and GPU algorithm acceleration for 3D and machine vision. 6. ACADEMIC BACKGROUND UNDERGRADUATE STUDIES Institution From To Diploma Date Speciality FIMEE Universidad de Guanajuato Engineering 15 June 1990 Communications and Electronics MASTERS Institution From To Diploma Date Speciality FIMEE Universidad de Guanajuato M. Eng. 19 June 1992 Instrumentation and Digital Systems PH.D. Institution From To Diploma Date Speciality Université Laval, Quebec, PQ. Canada Ph.D. 27 February 1998 Electrical Engineering (VLSI for Computer Vision) Miguel Octavio Arias Estrada, Ph.D. Page 1 of 18

2 PROFESSIONAL SOCIETIES IEEE member since 1990 IEEE member number: # Member of the Computer Society ACM member since 2011 ACM member # Member of the Siggraph SIG PROFESSIONAL INTERESTS Computer Vision Sensors, Smart Cameras, FPGA and GPU algorithm acceleration for Computer Vision, Bioinformatics and Neural Networks. High-tech entrepreneurship. 7. PREVIOUS POSITIONS Work positions Period Institution Position Field Jul Jun 1992 FIMEE Elctronics Eng. Dept. University of Guanajuato Salamanca, Gto. Mexico Lecturer Digital Systems Design, Microprocessors May Aug 1997 Sep Jul 1998 Electrical and Computer Engineering Dept. Université Laval Quebec, PQ. Canada Adjoint Professor Researcher Associate Professor Researcher VLSI teaching. Student advisor, FPGA platform for vision sensors. Aug Dec 2001 Jan Jun 2006 Jul 2006 Present Computer Science Dept. INAOE (National Institute for Astrophysics, Optics and Electronics) Tonanzintla, Puebla. Mexico Associate Researcher, Level C Titular Researcher, Level A Titular Researcher, Level B Teaching graduate courses, MSc and PhD graduate student advisor, project proposal and managment, conference organization. Research during formative years Period Institution Position Field Jul -Dec 1990 Optics Research Center (CIO). León, Gto. Mexico Professional Service Digital sequencer implementation fora thin film deposition machine. Jan - Jun 1990 FIMEE Electronics Dept. U. of Guanajuato Salamanca, Gto. Mexico Engineering Thesis Development system for a MC6803 microcontroller and a ROM emulator Sep Jun1992 FIMEE Electronics Dept. U. of Guanajuato Salamanca, Gto. Mexico M.Eng. Thesis Voice recognition using digital signal processing Digital audio acquisition system using the ADSP-2100 processor Sep 1992 Jun 1997 Computer Vision and Systems Laboratory Université Laval Quebec, PQ. Canada Ph.D. Tesearch Image motion sensor using focal plane processing with mixed-mode circuits. Tools used: Cadence, Synopsys, VHDL modeling. Technologies: 1.2 µm CMOS, 0.8 µm BiCMOS and 0.35 µm CMOS Miguel Octavio Arias Estrada, Ph.D. Page 2 of 18

3 8. TEACHING EXPERIENCE Course Institution/ Level Period Program Parallel Computing with GPUs INAOE M.Sc. Jan May 2011, 2012, 2013 Pattern Recognition ViBot program, U. of Burgogne, France M.Sc. Oct. 2006, Oct Invited professor. Digital System Design with FPGAs INAOE M.Sc. Jan. May. 1999, Jan. May Jan. May. 2001, Jan. May Jan. May. 2003, Jan. May Jan. May. 2005, Jan. May Jan. May. 2007, Jan. May Computer Architecture INAOE M.Sc. Sept. Dec. 1998, Sept. Dec Sept. Dec. 2000, Sept. Dec Sept. Dec Research seminar INAOE M.Sc. Jan. May. 1999, Jan. May Sept. Dec. 2002, Jan. May 2004 Computer Vision INAOE Ph.D. Summer 1999 Neural Networks INAOE Ph.D. Summer 1999, Jan. May Digital Systems and reconfigurable INAOE Ph.D. Sept Dec architectures Parallel and distributed processing INAOE Ph.D. Jan. May applied to computer vision Evolvable computing INAOE Ph.D. Jan. May HW/SW architectures for real-time video processing INAOE M.Sc./Ph.D. Summer 2000, Summer 2001 Summer 2002, Summer 2003 Reconfigurable computing INAOE Ph.D. Jan. May Introduction to robotics INAOE M.Sc. Jan. May Dynamic vision: stabilization and INAOE M.Sc. Summer 2001 tracking Parallel Computing INAOE M.Sc. Jan. May Tracking, stabilization and pointing devices INAOE Naval instrumentation certificate Digital instrumentation systems INAOE Naval instrumentation certificate VLSI Systems Introduction to VLSI Systems Digital Instrumentation Digital Electronics I Logic Design with Microprocessors 16-bit Microprocessors Linear IC laboratories Electrical Eng. Dept. Université Laval Quebec, PQ Canada Electrical Eng. Dept. Université Laval Quebec, PQ Canada FIMEE, Electronics U. of Guanajuato FIMEE, Electronics U. of Guanajuato FIMEE, Electronics U. of Guanajuato FIMEE, Electronics U. of Guanajuato FIMEE, Electronics U. of Guanajuato Graduate / undergraduate Graduate / undergraduate Jan. May 2004 Jan. May 2003 Jan. May 1997, Jan. May 1998 Aug.-Dec. 1996, Aug.-Dec 1997 Undergraduate Sep.-Dec. 1990, Sep.-Dec 1991, Apr.-Jun Undergraduate Jan.-Mar Undergraduate Jan.-Mar. 1991, Jul.-Sep Undergraduate Apr.-Jun Undergraduate Sep.-Dec 1991, Jan.-Mar. 1992, Apr.-Jun Miguel Octavio Arias Estrada, Ph.D. Page 3 of 18

4 9. SCIENTIFIC PRODUCTION 9.1 PUBLICATIONS IN JOURNALS M. Arias-Estrada, M. Tremblay, D. Poussart, A Focal Plane Architecture for Motion Computation, Journal of Real-Time Imaging, Special Issue on Special-Purpose Architectures for Real-Time Imaging, Vol. 2, No. 6, Dec. 1996, pp Miguel Arias-Estrada, César Torres-Huitzil, "A Real-time FPGA Architecture for Computer Vision," Journal of Electronic Imaging (SPIE IS&T), Vol 10, No. 1, January 2001, pp M. Arias-Estrada, L. Altamirano Robles, C. Torres Huitzil, S. Maya Rueda. "Diseño de Circuitos Combinacionales con Algoritmos Genéticos", aceptado en Revista Soluciones Avanzadas. Número especial en Cómputo Evolutivo, A.B. Flores, L.A. Robles, M.O. Arias, J.A. Ascencio. Small metal nanoparticles recognition using digital image analysis and high resolution microscopy, Micron 34, 2003, pp César Torres Huitzil and Miguel Arias Estrada, Real-time image processing in a small systolic FPGA architecture, SPIE International Technical Group Newsletter, Special Issue on Smart Image Acquisition and Processing. Vol. 14, No.1, January pp Cesar Torres Huitzil, Miguel Arias Estrada, "Real-time Image Processing with a Compact FPGA-based Systolic Architecture", Journal of Real-time Imaging, Elsevier, Vol. 10, pp Cesar Torres Huitzil, Miguel Arias Estrada, "FPGA-based Configurable Systolic Architecture for Real-time Windowbased Image Processing", EURASIP Journal on Applied Signal Processing, Special Issue on Machine Perception on a Chip. No. 7, pp J. G. Velásquez-Aguilar, G. Toker, A. Zamudio-Lara and M. Arias-Estrada. Visualization of a supersonic air micro jet by methods of dual-hologram interferometry, Journal of Experiments in Fluids. Springer Publisher. (2007) 42: ISSN: , Impact factor: G. Saldaña and M. Arias-Estrada, Compact FPGA-based systolic array architecture suitable for vision systems, Int. Journal of High Performance Systems Architecture, Vol 1, No 2, pp ISSN (Online): ISSN (Print): , Impact factor: P. Sánchez-Sánchez, F. Reyes-Cortés, A. Michua-Camarillo, J. Cid-Monjaraz, M. Arias-Estrada. Control and simulation of a robot of two degrees of freedom (Implementation of a new control algorithm), International Journal of Mathematics and Computers in Simulation, Vol. 1, Issue 4, pp ISSN: , Impact factor: Medina-Melendrez, M.; Arias-Estrada, M., Castro, A. Input and/or Output Pruning of Composite Length FFTs Using a DIF-DIT Transform Decomposition, IEEE Transactions in Signal Processing, vol 57, no. 10, Oct. 2009, pp ISSN: X, Impact factor: Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez and Miguel Arias-Estrada. Parallel Processor for 3D Recovery from Optical Flow," International Journal on Reconfigurable Systems (IJRC), vol. 2009, Article ID , 11 pages, doi: /2009/ ISSN: , Impact factor: N/A Carlos Polanco Gonzalez, Marco Aurelio Nuño Maganda, Miguel O Arias Estrada, Gabriel del Rio, "An FPGA implementation to detect selective cationic antibacterial peptides," in PLoS ONE. 6/11 ISSN : , Impact factor: Leonardo Chang, Jose Hernandez-Palancar, L. Enrique Sucar, Miguel Arias-Estrada, FPGA-based Detection of SIFT Interest Keypoints, accepted on the Journal of Machine Vision Systems and Applications, Springer, ISSN: (print version) ISSN: (electronic version) 15. Modesto Medina-Melendrez, Albertina Castro,and Miguel Arias-Estrada, Using an aliasing operator and a single discrete Fourier transform to down-sample the Fresnel transform, Optics Express, Vol. 20, No. 8, Apr pp ISSN: , 2010, ISI Impact Factor: Maria-Luisa Rosas and Miguel-Octavio Arias, Integrated three-dimensional reconstruction using reflectance fields, International Journal of Computer Science Issues (IJCSI), Vol. 9, Issue 1, No 3, Jan pp ISSN: Miguel Octavio Arias Estrada, Ph.D. Page 4 of 18

5 Garcia-Ordaz D., Arias-Estrada M.,Nuño-Maganda M., Polanco C. and Del Rio G., An FPGA vs GPU approach for accelerating the computation of Selective Cationic Antibacterial Peptides, Plos One Under preparation. To be submitted Jan Mario Alberto Mendoza-Bárcenas, Esaú Vicente-Vivas, Miguel Arias-Estrada, FPGA platform for development of Stabilization and Attitude Control Technology for Small Satellites, Journal of Small Satellites. To be submitted Dec Ma Luisa Rosas-Cholula, Patrick Hebert, Denis Laurendeau, Miguel Arias-Estrada, Three-dimensional reconstruction and appareance of objects 4D by integrating reflectance fields and visual hull, Machine Vision and Applications (MVAP). Under preparation. To be submitted February BOOKS AND CHAPTERS IN BOOKS 1. Griselda Saldaña-González and Miguel Arias-Estrada, FPGA based acceleration for image processing applications, chapter in book: Image Processing, Book Chapter, invited author. Editor: Dr. Vedran Kordic, Edit. In-Tech. Published Dec ISBN G. del Rio, M. Arias-Estrada, C. Polanco Gonzalez, The use of dedicated processors to accelerate the identification of novel antibacterial peptides, invited chapter collaboration in Frontiers in Computational Chemistry, Bentham ebooks. To be published in Under preparation. To be submitted Dec Miguel Octavio Arias Estrada, Ph.D. Page 5 of 18

6 9.3 PUBLICATIONS IN ARBITERED CONFERENCES WITH MEMORY IN EXTEND R. Romero Troncoso, M. Arias-Estrada, O. Ibarra Manzano, Simulador ROM, Electro 90, XII Reunión Académica de Ing. Electrónica, Chihuahua, Chih. Mexico. Oct ISSN , pp M. Arias-Estrada, J. Rivera Gonzalez, L. Martínez Rizo, Tarjeta digitalizadora de audio para reconocimiento de voz, CIECE 92 (2o. Congreso Interuniversitario de Electrónica, Computación y Eléctrica), Guanajuato, Gto., México, Mayo pp M. Arias-Estrada, Interfaz paralela de Entrada/Salida a través del puerto paralelo, CIECE 92 (2o. Congreso Interuniversitario de Electrónica, Computación y Eléctrica), Guanajuato, Gto., México, Mayo pp M. Arias-Estrada, R. Jaime-Rivas, Reconocimiento de objetos planos utilizando redes neuronales, IEEE Mexicon 92. Guadalajara, Jalisco, Oct pp M. Arias-Estrada, M. Tremblay, D. Poussart, Computational Motion Sensors for Autoguided Vehicles, 30th International Symposium on Automotive Technology & Automation (ISATA'97), Robotics, Motion and Machine Vision in the Automotive Industries. Florence, Italy, June 1997, pp M. Arias-Estrada, M. Tremblay, D. Poussart, A Motion Vision Sensor Architecture with Asynchronous Self-Signalling Pixels, in CAMP 97 (Computer Architectures for Machine Perception), Boston, MA, Oct. 1997, pp M. Arias-Estrada, Motion Camera based on a Custom Vision Sensor and an FPGA architecture, AFPAEC 98 Advanced Focal Plane Arrays and Electronic Cameras, Zurich, Suiza, May 1998, pp M. Arias Estrada, A. Lecerf, Cámaras Inteligentes para la Visión por Computadora, Taller de Inteligencia Artificial (TAINA 98). México, D.F., Nov pp C. Torres-Huitzil, M. Arias-Estrada, Arquitectura FPGA para la extracción en tiempo real de bordes y esquinas de una imagen, Encuentro Nacional de Computación ENC 99 Memorias, Taller de Graficación, Visión y Robótica. Septiembre 1999, Pachuca, Hgo. México Ref. 719, 6 paginas Selene Maya, Rocio Reynoso, Cesar Torres, Miguel Arias-Estrada, "Compact Spiking Neural Network Implementation in FPGA". Field Programmable Logic Conference (FPL'2000). Villach, Austria. Aug , 2000, Lecture Notes in Computer Science Vol Springer Verlag. R. Hartenstein, H. Grünbacher (Eds.) pp M. Arias-Estrada, C. Torres-Huitzil, Real-time FPGA Architectures for Computer Vision. SPIE Electronic Imaging 2000 Photonics West, dedicated conference on Machine Vision Applications in Industrial Inspection VIII. Proceedings of SPIE, Vol San Jose, CA jan pp A. Lecerf, D. Ouellet, M. Arias-Estrada, Computer Vision Camera with embedded FPGA processing. SPIE Electronic Imaging 2000 Photonics West, dedicated conference on Machine Vision Applications in Industrial Inspection VIII. Proceedings of SPIE, Vol San Jose, CA jan pp L. Altamirano-Robles, M.Arias-Estrada, S. Alviso-Quibrera, A. Lopez-Lopez, Sub-millimeter bolt location in car bodywork for production line quality inspection. SPIE Electronic Imaging 2000 Photonics West, dedicated conference on Machine Vision Applications in Industrial Inspection VIII. Proceedings of SPIE, Vol San Jose, CA jan pp M. Arias-Estrada, César Torres-Huitzil. Sistemas inteligentes en un chip utilizando FPGAs: Aplicaciones a la visión por computadora, X Congreso Internacional de Electrónica, Comunicaciones y Computadoras, CONIELECOMP Cholula, Pue. Feb pp S. Alviso-Quibrera, L. Altamirano-Robles, M. Arias-Estrada. Localización Milimétrica de Pernos en Pisos de Carrocerías de Automóviles Usando Técnicas de Análisis Digital de Imágenes, X Congreso Internacional de Electrónica, Comunicaciones y Computadoras, CONIELECOMP Cholula, Pue. Feb pp C. Carbajal, D. Poussart, M. Arias Estrada. "Síntesis de la Arquitectura VLSI del Detector de Bordes de Sobel", VI Iberchip Workshop, Sao Paulo, Brasil, marzo pp Juan Jaime Vega, Rocio Reynoso, Miguel Arias Estrada, Leopoldo Altamirano Robles, "Bragg Curve identification using a neural network," International Joint Conference on Neural Networks (IJCNN'2000). Como, Italy, July, 2000, pp. IV Cesar Torres-Huitzil, Miguel Arias-Estrada, "An FPGA Architecture for High Speed Edge and Corner Detection." Computer Architectures for Machine Perception (CAMP'2000). Padua, Italy, Sept. 2000, pp Miguel Arias Estrada, Roberto García de Campo, "An FPGA based Motion Computation Architecture for Real-Time". Visual 2000 conference. Mexico, D.F. Sept E. Turenne, M. Arias-Estrada, D. Poussart, "Motion Computation using a Smart Sensor". Visual 2000 conference, Mexico, D.F. Sept Miguel Arias-Estrada, Juan M. Xicotencatl, Multiple Stereo Matching using an Extended Architecture, FPL 2001 (Field Programmable Logic conference), Belfast, Ireland. Aug Lecture Notes in Computer Science Vol Springer Verlag. G. Brebner, R. Woods (Eds.) pp Miguel Arias-Estrada, Juan M. Xicotencatl, A Real-time FPGA based Architecture for Stereo Vision, SPIE Electronic Imaging 2001 Photonics West, dedicated conference on Real Time Imaging V. Proceedings of SPIE, Vol San Jose, CA. Jan pp L. Altamirano-Robles, M. Arias-Estrada, A. López-López, R. Lemuz-López. Visual system for automatic car registration, SPIE Electronic Imaging 2001 Photonics West, dedicated conference on Machine Vision Applications in Industrial Inspection IX. Proceedings of SPIE, Vol San Jose, CA. Jan pp Miguel Octavio Arias Estrada, Ph.D. Page 6 of 18

7 24. Víctor M. Meraz Ochoa, Miguel O. Arias Estrada. Sistema Genérico basado en FPGA para el Procesamiento en Tiempo Real de la Visión por Computadora. XI Congreso Internacional de Electrónica, Comunicaciones y Computadoras, CONIELECOMP Cholula, Pue. Feb. 2001, Juan Carlos Tejeda Yépez, Miguel Arias Estrada, Arquitectura FPGA para convolución de imágenes en tiempo real, XI Congreso Internacional de Electrónica, Comunicaciones y Computadoras, CONIELECOMP Cholula, Pue. Feb. 2001, pp M. Arias-Estrada, C. Torres Huitzil, S. Maya Rueda, Arquitecturas basadas en FPGA para la Visión por Computadora, CICINDI 2001 (3rd. International Conference on Control, Virtual Instrumentation and Digital Systems), México, D.F. Aug pp A. Espinosa Manzo, A. López López, M. Arias Estrada, Implementing Hidden Markov Models in a Hardware Architecture, Encuentro Nacional de Computación. ENC 2001, Aguascalientes, Ags pp J. Xicotencatl, M. Arias-Estrada, "Procesamiento estéreo en tiempo real con máquinas de estado utilizando un FPGA", TIARP 2001 (Taller Ibero Americano de Reconocimiento de Patrones). México, D.F., Octubre pp Miguel Arias-Estrada, C. Torres-Huitzil, S. Maya-Rueda. Remote hardware reconfigurable robotic camera, Intelligent Robots and Computer Vision XX. Proc. SPIE Vol. 4572, Photonics Boston. Boston, MA Oct pp M. Arias E., E. Rodriguez-Palacios, FPGA architecture for a visual tracking system, FPL 2002 (Field Programmable Logic conference), Lecture Notes in Computer Science 2438, Montpellier (La Grande-Motte) France. Sept pp C. Torres-Huitzil, M. Arias-Estrada. Reconfigurable vision system for real-time applications, SPIE Electronic Imaging 2002 Photonics West, dedicated conference on Real Time Imaging VI. Proc. SPIE Vol. 4666, San Jose, CA. Jan pp Miguel Arias-Estrada, Selene E. Maya-Rueda, Cesar Torres-Huitzil. FPGA-based Architecture for Real-Time Motion Recovering, SPIE Electronic Imaging 2002 Photonics West, dedicated conference on Real Time Imaging VI. Proc. SPIE Vol. 4666, San Jose, CA. Jan pp Miguel Arias Estrada, Eric Turenne, Denis Poussart, Marc Tremblay, Integrated motion computation sensor, IOS special session at IEEE Sensors Orlando, Fl. June B. Cante Michcol, M. Arias Estrada, Arquitectura hardware para etiquetado de bordes en una imagen binaria, II Congreso Nacional de Electrónica, BUAP, pp. S1-SD A. Espinoza Manzo, M. Arias Estrada, A. López López. Arquitectura Hardware para modelos ocultos de Markov, II Congreso Nacional de Electrónica, BUAP, pp. S6-FMC C. Torres Hutzil, S. Maya-Rueda, M. Arias-Estrada. A Reconfigurable Vision System for Real Time Applications. IEEE International Conference on Field-Programmable Technology (FPT-2002). Hong Kong, HK. Dec pp Aldrin Barreto, Leopoldo Altamirano, Miguel Arias Estrada, Jorge A. Ascencio, Luis C. Longoria, Reconocimiento de Nanopartículas usando Análisis Digital de Imágenes, Mexican International Conference on Artificial Intelligence, MICAI/TAINA 2002, Mérida, Yuc. México, Abril Iván Olivera Romero, Leopoldo Altamirano Robles, Miguel Arias Estrada, Segmentación temporal aplicada a la detección de objetos en movimiento en imágenes infrarrojas, Mexican International Conference on Artificial Intelligence, MICAI/TAINA 2002, Mérida, Yuc. México, Abril Selene Maya-Rueda, Miguel Arias-Estrada, "FPGA Processor for Real-time Optical Flow Computation", 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lecture Notes in Computer Science, Vol. 2778, 1st - 3rd Sept. 2003, in Lisbon, Portugal. pp Cesar Torres-Huitzil, Miguel Arias-Estrada, " Configurable Hardware Architecture for Real-time Window-based Image Processing", 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lecture Notes in Computer Science, Vol. 2778, 1st - 3rd Sept. 2003, in Lisbon, Portugal. pp Juan M. Xicotencatl, Miguel Arias Estrada, "FPGA High Density Spiking Neural Network Array", 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lecture Notes in Computer Science, Vol. 2778,1st - 3rd Sept. 2003, in Lisbon, Portugal. pp Moises Pérez-Gutiérrez, Miguel Arias Estrada, Biblioteca de Componentes Hardware Software, Congreso Internacional de Electrónica Comunicaciones y Computadoras CONIELECOMP Puebla, Pue pp Erika Vera Díaz, Miguel Arias Estrada, Herramienta para el realce de imágenes arqueológicas, Congreso Internacional de Electrónica Comunicaciones y Computadoras CONIELECOMP Puebla, Pue pp Francisco Javier Enríquez Aguilera, Miguel O. Arias Estrada, Coprocesador basado en FPGA para Algoritmos de Seguimiento de Blancos, Congreso Internacional de Electrónica Comunicaciones y Computadoras CONIELECOMP Puebla, Pue pp /a. 45. Selene E. Maya-Rueda, Cesar Torres-Huitzil, Miguel O. Arias-Estrada, Real-Time FPGA-based Architecture for Optical Flow Computation, CAMP2003, IEEE Sixth International Workshop on Computer Architecture for Machine Perception, New Orleans, LA., May 11-14, Marco Aurelio Nuño Maganda, Miguel Arias Estrada, Arquitectura Hardware para el Seguimiento de Objetos utilizando Procesamiento Piramidal, Avances en la ciencia de la computación en México, CORE México, D.F., pp Miguel Morales-Sandoval, Moisés Pérez-Gutiérrez, Claudia Feregrino-Uribe, Miguel Arias-Estrada. Arquitectura FPGA para un Procesador Matricial, 1er Taller de Cómputo Reconfigurable y FPGAs. IV Congreso Internacional de Ciencias de la Computación (ENC 2003), Apizaco, Tlax. Sept. 8 a 12, pp Marco A. Nuño Maganda, Miguel Arias Estrada, Claudia Feregrino Uribe. Implementación Hardware de Aplicaciones de la Pirámide, 1er Taller de Cómputo Reconfigurable y FPGAs. IV Congreso Internacional de Ciencias de la Computación (ENC 2003), Apizaco, Tlax. Sept. 8 a 12, pp Miguel Octavio Arias Estrada, Ph.D. Page 7 of 18

8 49. I. Bravo, J.L. Lázaro, R. Rivera, J.J. Heras, M.O. Arias, Algoritmos para la multiplicación de máscaras sobre imágenes, 1er Taller de Cómputo Reconfigurable y FPGAs. IV Congreso Internacional de Ciencias de la Computación (ENC 2003), Apizaco, Tlax. Sept. 8 a 12, pp Carlos A. Díaz Hernández, Luis D. López Gutiérrez, Miguel Arias Estrada, Claudia Feregrino Uribe, René Cumplido Parra. Implementación FPGA del cálculo de profundidades en la recuperación de 3D usando luz estructurada, 1er Taller de Cómputo Reconfigurable y FPGAs. IV Congreso Internacional de Ciencias de la Computación (ENC 2003), Apizaco, Tlax. Sept. 8 a 12, pp Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, Claudia Feregrino-Uribe, Three Video Applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization, IEEE International Conference on Field- Programmable Technology (FPT 03), Tokyo, Japan, Dec pp David Tenorio Pérez, Miguel Arias Estrada, Arquitectura Hardware para la Detección Subpixel de Bordes en Tiempo Real, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp Mónica W. Cruz-Ramírez, Miguel Arias-Estrada, Arquitectura Hardware para Creación de Mosaicos de Video en Tiempo Real, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp Juan M. Xicoténcatl, Miguel Arias-Estrada, Implementación FPGA del problema del Agente Viajero Utilizando Celdas con Conectividad Ocho, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp Liz Castillo-Jiménez, Miguel Arias-Estrada, Corrección Radial y Perspectiva de Video con FPGAs, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp Victor Rosales-Hernández, Marco Nuño-Maganda, Miguel Arias-Estrada, URANUS: Una Herramienta para Prototipar Algoritmos de Procesamiento de Video, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp Moisés Pérez-Gutiérrez, Miguel Arias-Estrada, Library of Hardware/Software Components for Remote Secure Configuration, 2004 International Conference on Reconfigurable Computing and FPGAs (ReConFig 04). Colima, Col., Sept 2004., pp M. Arias Estrada, F. Enríquez Aguilera, R. Pérez Blanco, Coprocesador de correlación basado en FPGA, IV Congreso Internacional Electrónica y Tecnologías de Avanzada. Instituto de Investigación y Desarrollo de Tecnologías Aplicadas, U. de Pamplona. Norte de Santander, Colombia. Vol. 1, No. 5, 2005, pp M. Arias-Estrada, G. Saldaña, M. Nuño, V. Rosales, C. Torres-Hutzil, Real-time Computer Vision using FPGA based Processing: Overview of INAOE Activities, Rétines Electroniques, ASIC-FPGA et DSP pour la vision et le traitement d images en temps réel, READ2005, Institut National de Télécommunications, Evry, France 1-3 june, pp Gerardo Sosa, Miguel Arias-Estrada, 3D recovery with free hand camera motion, Mexican International Conference in Computer Science, ENC Puebla, Pue., Sept pp Liz Castillo, Miguel Arias-Estrada, Super-resolution with integrated radial distortion correction, Mexican International Conference in Computer Science, ENC Puebla, Pue., Sept 2005., pp Griselda Saldaña, Miguel Arias-Estrada, FPGA-based customizable systolic architecture for Image Processing Applications, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 05). Puebla, Pue., Sept p3 (8 pages) 63. Marco Nuño-Maganda, Miguel Arias-Estrada, FPGA-based bicubic interpolation architecture for digital image scaling, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 05). Puebla, Pue., Sept p1 (8 pages) Rafael Lemuz-López and Miguel Arias-Estrada, A domain reduction algorithm for incremental projective reconstruction, In Proc. Int. Symposium on Visual Computing (ISVC'2006), Lake Tahoe, Nevada, LNCS Vol. 4292, November Springer. pp Rafael Lemuz-López and Miguel Arias-Estrada, Iterative closest SIFT formulation for robust feature matching, In Proc. Int. Symposium on Visual Computing (ISVC'2006), Lake Tahoe, Nevada, LNCS Vol. 4292, November Springer. pp Alicia Morales-Reyes, Miguel Arias-Estrada, Stereo Analysis Extension based on BRDF Reciprocity, Proceedings of the 16th IEEE Int. Conf. On Electronics, Communications and Computers (CONIELECOMP 2006). pp Griselda Saldaña and Miguel Arias-Estrada, Real Time FPGA-based Architecture for Video Applications, International Conference on Reconfigurable Computing and FPGAs, RECONFIG'06, Universidad Autnoma de San Luis Potos (UASLP), Septiembre pp Esteban O. García, René Cumplido, Miguel Arias, Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves Generator, 3rd International Conference on Electrical and Electronics Engineering (ICEEE 2006), Veracruz, Ver. Sept 6-8, pp Griselda Saldaña and Miguel Arias-Estrada, Customizable FPGA-Based Architecture for Video Applications In Real Time, 2006 IEEE International Conference on Field Programmable Technology, Bangkok Thailand. December pp Velasquez-Aguilar, J.G.; Mayorga-Cruz, D.; Zamudio-Lara, A.; Arias-Estrada, M.O.; Real-time displacements measurement using FPGA and interferometry, Multiconference on Electronics and Photonics, MEP Nov Page(s): Miguel Octavio Arias Estrada, Ph.D. Page 8 of 18

9 Marco Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, An Efficient Scalable Parallel Hardware Architecture for Multilayer Spiking Neural Networks, IEEE Southern Conference on Programmable Logic (SPL 07), Mar del Plata, Argentina, Febrero 2007, pp V. Rosales-Hernandez, L. Castillo-Jimenez, G. Viveros-Velez, V. Zuñiga-Grajeda, A. Treviño-Torres, M. Arias-Estrada. "URANUS: a rapid prototyping tool for FPGA embedded computer vision," 8th International Conference on Quality Control by Artificial Vision (QCAV 2007). Le Creusot, France. May 23-25, Marco Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil. High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs, IEEE International Conference on Field Programmable Technology (ICFPT- 07). Kitakyushu, Japan, pp Saldana, Griselda, Arias-Estrada, Miguel, Compact FPGA-based systolic array architecture suitable for vision system, Proceedings of the 4th International Conference on Information Technology: New Generations (ITNG2007), Las Vegas Nevada, USA, April 2007, pp ISBN: Saldaña, Griselda, Arias-Estrada, Miguel, Compact FPGA-based systolic array architecture for motion estimation using full search block matching, Southern Conference on Programmable Logic 2007 (SPL 07), Mar de Plata, Argentina, February, 2007, pp ISBN: Arias Estrada, M.O.; Espinosa Manzo, A.; Cruz Ramirez, M.W.; Colin Robles, J.A.; Mathematical model of the SS without considering not conservative forces, Electronics, Robotics and Automotive Mechanics Conference, CERMA Sept Page(s): J.C. Moctezuma Eugenio, M. Arias Estrada, "Diseño de una Plataforma FPGA con Linux Embebido para el Control de Robots Móviles", XIV Iberchip Workshop, Puebla-México, 2008 ISBN J.C. Moctezuma Eugenio, M. Arias Estrada, R.Cumplido Parra, "Arquitectura FPGA Parametrizable para Convolución de Imágenes", XIV Iberchip Workshop, Puebla-México, 2008 ISBN Rafael Lemuz-López and Miguel Arias Estrada, Ranking Corner Points by the Angular Difference between Dominant Edges, 6 th Int. Conf. on Computer Vision Systems ICVS LNCS May 12-15, 2008, p Cesar Torres-Huitzil, Bernard Girau, and Miguel Arias-Estrada. Biologically-inspired digital architecture for a cortical model of orientation selectivity, in Vera Kurkov a, Roman Neruda, and Jan Koutn ık, editors, 18th International Conferenceon Artificial Neural Networks - ICANN (2), LNCS Vol. 5164, pages Springer, M. Alejandra Menéndez O, D. Sosa G, Miguel Arias-Estrada, A. Espinosa M, J. E. Lara R, Creation of a 3D Robot Model and its Integration to a Microsoft Robotics Studio Simulation, Advanced Techniques in Computing Sciences and Software Engineering, Volume II of the proceedings of the 2008 International Conference on Systems, Computing Sciences and Software Engineering (SCSS), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering, CISSE 2008, Bridgeport, Connecticut, USA; 01/ José Hugo Barrón-Zambrano, Fernando Martin del Campo-Ramírez, Miguel Arias-Estrada, "Parallel Processor for 3D Recovery from Optical Flow," International Conference on Reconfigurable Computing and FPGAs - RECONFIG, pp Juan Carlos Moctezuma Eugenio and Miguel Arias Estrada, Hardware/Software FPGA Architecture for Robotics Applications," 5th International Workshop on Applied Reconfigurable Computing, ARC2009. Springer Verlag LNCS 5453, Karlsruhe, Germany. March 16-18, pp Marco Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Bernard Gireau, A population coding hardware architecture for spiking neural networks applications, V Southern Conference on Programmable Logic (SPL 09), Sao Carlos, Brazil, April 1-3, pp Marco Aurelio Nuno-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Bernard Girau, Hardware Implementation of Spiking Neural Network Classifiers based on Backpropagation-based Learning Algorithms, Proceedings of International Joint Conference on Neural Networks, Atlanta, Georgia, USA, June 14-19, pp M. Medina-Melendrez, M. Arias-Estrada and A. Castro, Overflow Analysis in the Fixed-Point Implementation of the First-Order Goertzel Algorithm for Complex-Valued Input Sequences, in Proc. of the 52 nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2-5, 2009, pp M.A. Mendoza, Miguel Arias, Esaú Vicente, J.R. Córdova, Hugo Rodríguez, E. Vizcaíno, E.A. Jiménez, A. Ramírez, J.F. Osorio, Development and prelimirary results of one-axis FPGA based Attitude Control System, Workshop mexicano de cómputo reconfigurable y aplicaciones en educación e ingeniería, taller dentro de Reconfig Dec Marco Aurelio Nuño-Maganda, César Torres-Huitzil, and Miguel Arias-Estrada. A High Performance Hardware Architecture for Image Clustering using K-Means, In Proceedings 2011 World Congress on Engineering and Technology, volume 6, pages , Octubre ISBN Ma.Luisa Rosas Cholula, Miguel Arias-Estrada, Acceleration of the reflectance field acquisition using independent component analysis, Proceedings of the 16th IEEE Int. Conf. On Electronics, Communications and Computers (CONIELECOMP). Puebla, Mexico. Feb 27-29, M.A. Mendoza-Barcenas, E. Vizcaíno, E. Vicente-Vivas, M. Arias-Estrada, I. Mendoza, J.A. Colín,, Embedded attitude Miguel Octavio Arias Estrada, Ph.D. Page 9 of 18

10 control system for the educative satellite SATEDU, Proceedings of the 16th IEEE Int. Conf. On Electronics, Communications and Computers (CONIELECOMP). Puebla, Mexico. Feb 27-29, I. Ojog, M. Arias-Estrada, m3dicom: A Platform for Mobile DICOM Visualization Based on X3D, etelemed 2012, The Fourth International Conference on ehealth, Telemedicine, and Social Medicine. Valencia, Spain. Jan 30, 2012, pp ISBN: Modesto Medina-Melendrez, Miguel Arias-Estrada, Albertina Castro, Using a Scaling Factor in O(1/N) for the Fixed- Point Implementation of the Second-Order Goertzel Filter, accepted for publication at IEEE International Symposium on Circuits and Systems, ISCAS Seoul, Korea. May 20-23, pp Nuno-Maganda, M.A.; Arias-Estrada, M.; Torres-Huitzil, C.; Aviles-Arriaga, H.H.; Hernandez-Mier, Y.; Morales- Sandoval, M., A Hardware Architecture for Image Clustering Using Spiking Neural Networks, 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp DOI: /ISVLSI G. Rosas, M. Arias-Estrada, Mexbox: a platform for FPGA embedded computing, VIII Southern Programmable Logic Conference (SPL 2012), Designer Forum. Bento Gonçalves, Brasil, March 20-23, Paper award as Best Paper in Designers Forum. 95. Garcia-Ordaz D., Arias-Estrada M.,Nuño-Maganda M., Polanco C. and Del Rio G., ACCELERATION OF SELECTIVE CATIONIC ANTIBACTERIAL PEPTIDES COMPUTATION: A COMPARISON OF FPGA AND GPU APPROACHES, 3 rd International Supercomputing Conference in Mexico, ISUM Guanajuato, Gto. March 14-16, L. Chang, M. Arias-Estrada, L. E. Sucar, J. Hernández-Palancar, Local Invariant Shape Feartures for Object Recognition Robust to Occlusion, submitted to CVPR (IEEE 26 th conference on Computer Vision and Pattern Recognition Conference), Portland, Oregon, June 23-28, L. Chang, M. Arias-Estrada, L. E. Sucar, J. Hernández-Palancar, Efficient Local Shape Features Matching using CUDA, submitted for publication at GPU Technology Conference San Jose, CA. March 18-21, E. León Sandoval, L. Barbosa Santillán, M. Arias-Estrada, Hybrid cluster method for synthesizing data using GPUs, submitted for publication at GPU Technology Conference San Jose, CA. March 18-21, I. Ojog, M. Arias-Estrada, J A. Gonzalez, B. Flores, m3dicom: A Cloud Scalable Platform for DICOM Image Analysis as a Tool for Remote Medical Support, etelemed 2013, The Fifth International Conference on ehealth, Telemedicine, and Social Medicine. Nice, France. Accepted for publication. 9.4 PATENTS 1. Miguel Arias-Estrada, Detecteur de déplacement/imageur integré / Integrated Motion Vision Sensor, Canadian Patent CA Submitted July 9, Granted: Jan 10, Miguel Arias-Estrada, Integrated Motion Vision Sensor, US Patent Submitted July 9, Granted: June 26, Miguel Arias-Estrada, Alicia Morales Reyes, Maria Rosas Cholula, Gerardo Sosa Ramírez, FAST THREE DIMENSIONAL RECOVERY METHOD AND APPARATUS, US Patent Publication, USPTO. US 2010/ , Granted, Published Nov 25, Granted with additional claims. US 8,121,352 B2, Feb 21, Miguel Arias-Estrada, Alicia Morales Reyes, Maria Rosas Cholula, Gerardo Sosa Ramírez, PROCEDE ET APPAREIL DESTINES A LA RESTAURATION TRIDIMENTIONNELLE RAPIDE / METHOD AND APPARATUS FOR RAPID THREE- DIMENSIONAL RESTORATION, Canadian Patent Application, CIPO, CA , Pending Miguel Arias-Estrada, Alicia Morales Reyes, Maria Rosas Cholula, Gerardo Sosa Ramírez, METHOD AND APPARATUS FOR RAPID THREE-DIMENSIONAL RESTORATION, European Patent Application, , Pending CITATIONS Number of citations: 344 Number of citations without self-citations: 292 Miguel Octavio Arias Estrada, Ph.D. Page 10 of 18

11 10. GRADUATE STUDENTS 10.1 M.Sc. Graduated Students Roberto García de Campo, Arquitectura Digital para el Cómputo en Tiempo Real del Movimiento en una Imagen, (Digital architecture for Real Time image motion computation, in Spanish), M.Sc. Thesis in Electronics, INAOE. Sept Juan Manuel Xicotencatl Pérez, Arquitectura Hardware de visión estéreo en tiempo real, (Digital architecture for Real Time Stereo Computation, in Spanish), M.Sc. Thesis in Electronics, INAOE. Oct Iraida Nikitin Timofeeva, Clustering algorithms for 3D data segmentation, (in English), M.Sc. Thesis in Computer Science, INAOE. Feb Juan Carlos Tejeda Yépez, Arquitectura FPGA para Filtrado de Imágenes en Tiempo Real, (Real Time Architecture for Image 2D Filtering based on Convolution, in Spanish), M.Sc. Thesis in Electronics, INAOE. May Janeth Cruz Enríquez, Sistema de Conteo Automático de Huevecillos de Mosca del Mediterráneo MECAS, (Automatic mediterranean fly eggs counting system, in Spanish), M.Sc. Thesis in Computer Science, INAOE. Dic Codirected with Dr. Leopoldo Altamirano Robles. 6. Victor Manuel Méraz Ochoa, Sistema basado en FPGA para el Desarrollo de Aplicaciones de Visión por Computadora en Tiempo Real, (FPGA based system for Real-Time Computer Vision Application Development, in Spanish), M.Sc. Thesis in Electronics, INAOE. Jun Eduardo Rodríguez Palacio, Co-procesador FPGA para Seguimiento Visual, (FPGA architecture for Real-Time Tracking based on edge and corner primitives, in Spanish), M.Sc. Thesis in Electronics, INAOE. Jul Bernardo Cante Michcol, Arquitectura hardware para etiquetado de bordes en una imagen binaria, (FPGA based architecture for edge labeling in real-time, in Spanish), M.Sc. Thesis in Electronics, INAOE. May Dario Cesar Peregrina Albores, Seguimiento de Objetos por medio de Visión Activa, (Active Vision for Object Tracking, in Spanish), M.Sc. Thesis in Computer Science, INAOE. May Codirected with Dr. Leopoldo Altamirano Robles and Dr. Olac Fuentes Chávez. 10. Iván Olivera Romero, Detección y Seguimiento de Objetos en Imágenes Infrarrojas Usando Información Temporal, (Object detection and tracking in infrared images using temporal information, in Spanish), M.Sc. Thesis in Computer Science, INAOE. Aug Codirected with Dr. Leopoldo Altamirano Robles. 11. Alejandro Espinosa Manso, Una Arquitectura Hardware para Modelos Ocultos de Markov, (A Hardware architecture for Hidden Markov Models, in Spanish), M.Sc. Thesis in Computer Science, INAOE. Ago Codirected with Dr. Aurelio López López. 12. Hugo Gómez García, Plataforma de Cámara Inteligente basada en un Sistema-en-Chip Configurable, (Smart Camera based on a Configurable System on a Chip, in Spanish), M.Sc. Thesis in Computer Science, INAOE. Nov Erika Vera Díaz, Herramienta para el Realce de Imágenes Arqueológicas, (Image enhancement tool for archeological image reconstruction, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Nov Francisco Javier Enríquez Aguilera, Coprocesador basado en FPGA para seguimiento de blancos en tiempo real, (Real-Time Visual tracking FPGA based coprocessor, in Spanish), M.Sc. Thesis in Electronics, INAOE, Mar Sergio Juarez Velasquez, Modelado Dinámico de Objetos en 3D, (Automatic 3D modeling recovery from stereo disparity images, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Nov Marco Aurelio Nuño Maganda, Una Arquitectura FPGA para el seguimiento de objetos utilizando procesamiento piramidal, (Object tracking FPGA architecture based on pyramidal reconstruction, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Jul Victor Hugo Rosales Hernández, Recuperación 3D de la Estructura de una Escena a partir del Flujo Optico, (3D recovery from optical flow, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb David Tenorio Pérez, Arquitectura Hardware para la Detección Subpixel de bordes en tiempo real, (FPGA architecture for subpixel edge and corner detection, in Spanish), M.Sc. Thesis in Electronics, INAOE, Mar Mónica Wendoly Cruz, Arquitectura Hardware para Construcción de Mosaicos en Tiempo Real, (FPGA based real-time mosaic construction, in Spanish), M.Sc. Thesis in Electronics, INAOE, Apr Moises Pérez Gutierrez, Biblioteca para reconfiguración remota de componentes hardware/software, (Component library for remote HW-SW reconfiguration of FPGA devices, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Gerardo Sosa Ramírez, Recuperación 3D con movimiento libre de la camara, (3D recovery with a free moving camera, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Liz Nicandi Castillo Jiménez, Creación de Mosaicos de Super Resolución con Tecnología FPGA, (Real-time superresolution image mosaics construction using FPGA technology, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Salvador Arroyo Díaz, Plataforma Reconfigurable Basada en FPGA para Procesamiento de Imágenes, (Reconfigurable FPGA platform for image processing applications, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Alicia Morales Reyes, Geometry Generalization for Stereo Recovery Based on BRDF Reciprocity, (in English), M.Sc. Thesis in Computer Science, INAOE, Feb Miguel Octavio Arias Estrada, Ph.D. Page 11 of 18

12 25. Maria Luisa Rosas Cholula, Rectificación radiométrica y geométrica de un sistema estéreo, (Radiometric and geometric rectification of a stereo system, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Adriana Hernández Camarillo, Recuperación en tiempo real del flujo óptico de una secuencia de video usando una arquitectura FPGA, (Real-time optical flow recovery using a dedicated FPGA based architecture, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Jan Sayde Alcantara Santiago. Arquitectura Sistólica para el Filtrado Espacial de Imágenes en Múltiples Orientaciones, (Systolic architecture for image spatial filtering in multiple orientations, in Spanish), M.Sc. Thesis in Computer Science, Codirected with Cesar Torres Huitzil. INAOE. Dec Victor Manuel García y García, Arquitectura basada en FPGA para la recuperación estéreo en tiempo real para una cámara inteligente, (FPGA based architecture for real-time stereo recovery in a smart camera, in Spanish), M.Sc. Thesis in Computer Science. INAOE. Feb Nestor Prado Vargas, Corrección geométrica, alineado y uniformidad de brillo para la construcción de un mosaico de imágenes proyectadas, (Geometric, alignment and illumination uniformity correction for projected mosaics of images, in Spanish), M.Sc. Thesis in Computer Science, INAOE, Feb Feliciano Acuña, Arquitectura FPGA para procesamiento de imágenes con redes neuronales de función de base radial, (FPGA implementation of radial-basis function neural networks for image processing, in Spanish), M.Sc. Thesis in Computer Science. Codirected with Cesar Torres Huitzil. INAOE. Mar Jose Hugo Barrón Zambrano, Procesador paralelo para la recuperación 3D a partir del flujo óptico, (Parallel processor for 3D recovery from optical flow, in Spanish), M.Sc. Thesis in Computer Science. INAOE. Dec Juan Carlos Moctezuma Eugenio, Plataforma FPGA para robótica móvil, (FPGA based platform for mobile robotics, in Spanish), M.Sc. Thesis in Computer Science. INAOE. Feb Leonardo Chang Fernández, Arquitectura Hardware para la Detección de Puntos de Interés del SIFT, (Hardware architecture for SIFT interest point detection, in Spanish), Co-directed with Dr. Enrique Sucar Succar (INAOE) and Dr. José Hernández Palancar (CENATAV-Cuba). M.Sc. Thesis in Computer Science. INAOE. Nov Victor Hugo Arroyo Domínguez. "Reconstrucción 3D de superficies metálicas especulares utilizando luz polarizada", (3D reconstruction of specular surfaces using polarization, in Spanish). M.Sc. Thesis in Computer Science. INAOE. Feb Ulises Aguirre. 3D from optical flow and visual cues. Work in progress. Estimated Sept Alberto Gonzalez. GPCA algebraic method applied to visual gesture recognition. Work in progress. Co-directed with Gustavo Rodriguez. Estimated Sept Ph.D. Graduated Students 1. Cesar Torres Huitzil, Reconfigurable Computer Vision System for Real-time Applications, (in English), Ph.D. Thesis in Computer Science, INAOE. Aug Juan Manuel Xicotencatl Pérez, Arquitectura genérica para hardware evolutivo basada en FPGA, (FPGA based architecture for evolvable hardware applications, in Spanish). Ph.D. Thesis in Computer Science, INAOE. Feb Griselda Saldaña, Flexible Systolic Architecture for Image Processing at Video Rate, (in English), Ph.D. Thesis in Computer Science, INAOE. Oct Rafael Lemuz López, Improved Algorithms for Incremental Self-calibrated Reconstruction from Video, (in English), Ph.D. Thesis in Computer Science, INAOE. April Marco Aurelio Nuño Maganda, A High Performance Hardware Architecture for Multilayer Spiking Neural Networks, (in English), Ph.D. Thesis in Computer Science, INAOE. Oct Modesto Guadalupe Medina Melendrez, Reformulation of the Fresnel Transform to Introduce Sampling and Recovery Region Control and its Acceleration, (in English), Ph.D. Thesis in Computer Science, INAOE. Jan J. Guadalupe Velázquez Aguilar, Arquitectura Hardware en FPGA, para la Reconstrucción y Evaluación de Hologramas Digitales, utilizando Interferometría Holográfica (in Spanish), co-directed with Dr. Alvaro Zamudio Lara, Universidad Autónoma del Estado de Morelos, Fac. De Ciencias Químicas e Ingeniería. Centro de Investigación en Ingeniería y Ciencias Aplicadas (CiiCap). Cuernavaca, Mor. Feb Ma Luisa Rosas Cholula. Three-dimensional reconstruction using reflectance fields, (Reconstrucción tridimensional usando campos de reflectancia). In English. Work in progress, estimated Jan Work in progress 9. Mario Alberto Mendoza Bárcenas, hardware-software partitioning for a microsatellite FPGA based attitude and control system, UNAM Engineering graduate program, codireted with Esaú Vicente Vivas (UNAM). Estimated Aug Leonardo Chang Fernandez, CLASIFICACION DE OBJETOS EN IMAGENES EN TIEMPO REAL USANDO CARACTERISTICAS LOCALES DE APARIENCIA Y FORMA, codirected with Enrique Succar (INAOE), Estimated Aug Omar Rodríguez, Counting People in Dense Scenarios using Sequences of Depth Images taken by Zenithal Cameras, codirected with Joaquín Salas (CICATA, IPN). Estimated Aug Miguel Octavio Arias Estrada, Ph.D. Page 12 of 18

13 10.3. PhD, MSc. Committee member Committee Accumulated total INAOE PhD 12 INAOE MSc 61 External PhD 3 External MSc 2 Miguel Octavio Arias Estrada, Ph.D. Page 13 of 18

14 11. RESEARCH AND DEVELOPMENT PROJECTS Leader of the following projects were I obtained the grant. Period Institution Project details Jan-Dec 1999 Conacyt I29900-A Integrated Digital Camera for Computer Vision Applications. Design of FPGA based platform for architecture and system research on computer vision. Installation project. $69,000 m.n. (US$7,200) granted Jan 2000 Dec 2001 Sept 1999 Aug 2000 Sept 2000 Aug 2001 Jan 2000 Dec 2001 March 2001 Dec 2001 Jan Dec 2003 Apr 2003 March 2005 May 2003 June 2008 May 2003 Apr 2005 Sep 2004 Aug 2006 May 2004 Feb 2008 Jan 2006 June Conacyt J32151-A Volkswagen de México Colegio de la Frontera Sur Secretaria de Marina y Armada de México INAOE SEMAR INAOE SEMAR Conacyt 42312Y Conacyt-SMAM (fondos sectoriales) Marina-2002-C Conacyt-SMAM (fondos sectoriales) Marina-2002-C Marina-2002-C Marina-2002-C Marina-2002-C Marina-2002-C GTMQ (Grupo de trabajo México- Quebec) SEP Conacyt-SMAM (fondos sectoriales) Marina Conacyt-SMAM (fondos sectoriales) Marina-2005-C05-16 Conacyt- Ciencia Básica Reconfigurable computing applied to Computer Vision. Use of FPGA and dynamic reconfiguration for Real Time computer vision applications. Young researcher project. $802,000 m.n. (US$80,000) granted LeoPernos. Automated bolt inspection system for robot welded bolts in the Jetta A4 bodywork. Advisor, and system concept and electrical design. MECAS. Computer vision based automatic counting system of Mediterranean fly eggs. Co-advisor of one MSc student. GARFIO. Design and development of a sensor positioning payload for surveillance and tracking using computer vision techniques. Portable Secure Communications System. Project head, five people team. Design and development of a proof of concept prototype for a portable communication secure system using an FPGA based encryption architecture. Internal project proposal for SEMAR Garfio 1.5. Scientific committee member for the development of two target director systems based on the previous Garfio 1.0 system. The system is being developed by the Engineering Center of INAOE, under the supervision of the Scientific committee. 3D Handheld scanner using FPGA technology. Development of 3D techniques based on high speed image processing in an FPGA based camera. $370, m.n. (US$33,600) granted SVA Airborne Surveillance System (Sistema de Vigilancia Aéreo, a.k.a. Garfio Aereo). Development of a high performance payload for airborne surveillance including self-stabilization and three image sensors: visible CCD, visible spotter, LWIR with 2-FOV. Team direction, around 15 people involved. $8 555, m.n. (US$ 777,770) granted Project coordinator, together with Dr. Leopoldo Altamirano. Coordination of the five projects granted to our research group. Garfio II Naval surveillance system SVA (Garfio AE) Airbone surveillance system Tactic console Network of consoles to monitor and control navy instruments Radar Development of a basic radar system Medical network Imagenology network for a navy hostpital Coordination of activities and resources. Around 80 people involved in all the projects. Integrated platform for 3D sensors research. Cooperation project with Dr. Patrick Hebert (Université Laval, Quebec, Canada). The idea is to combine our expertise in image processing using FPGA and their expertise in 3D modeling algorithms, in order to propose new 3D sensors. 8,000$cnd (US$ 5,400) granted, mainly for researchers and students mobility. IR Camera. Development of an IR camera module as a subsystem for surveillance applications $5 435, m.n. (US$481,000) granted. SLVA Light Airborne Surveillance System (Sistema Ligero de Vigilancia Aérea). Development of a light payload for helicopter airbone surveillance including self-stabilization and two image sensors: visible CCD, LWIR with 2- FOV. Team direction, around 20 people involved. $14 457,050 m.n. (US$ 1 314,300) granted 3D visualization and segmentation accelerated with CUDA technology for medical applications Exploration of DICOM based 3D segmentation using high parallel algorithms implemented on CUDA technology Under preparation Miguel Octavio Arias Estrada, Ph.D. Page 14 of 18

15 12. CONFERENCE AND ACADEMIC EVENTS ORGANIZATION Period Institution Achievements Sept 8-9, 2003 FPGA and mobile computing laboratory Computer Science INAOE FPGA workshop. As our initiative, the FPGA group of INAOE submitted a workshop proposal to the ENC 03. It was the most succesful and attended of all the workshops. There were around 30 attendants from Mexico and abroad. Details: Nov 2003 March 2004 Sept 20-21, 2004 Sept 20-22, 2004 Sept 26-30, 2005 FPGA and mobile computing laboratory Computer Science INAOE SMCC Univ. of Colima INAOE SMCC Univ. of Colima SMCC BUAP Short intensive 24-hour courses for academic and industry people who requires a fast hands-on introduction to VHDL and FPGA technology. The courses were given in the INAOE installations. At present there has been two courses with 20 attendants each. Information about the course can be found in the web page: ENC 04 workshops coordination, together with Dr. Alexander Gelbukh (CIC). As a consequence of the success of the FPGA workshop in the ENC 03, I was invited to coordinate the workshops in the 2004 conference. We have invited and coordinate 10 workshops that will take place in the ENC 04 (International Conference of Computer Science) to be held in Colima, sep More details: -> Talleres ReConFig 04 International Conference on Reconfigurable Computing and FPGAs As a consequence of the succes of the FPGA workshop in the ENC 03, our FPGA group decided to organize an international conference oriented to the latinamerican region, with a similar scope to FPL (Europe) or FPT (Asia) Details: -> Reconfig 04 President and general chair for the ENC 05 As a consequence of the ReConFig 04 conference, I was invited to coordinate the IEEE ENC2005 conference which is one of the major computer science conference in Mexico. The conference received around 300 participants from Mexico and abroad. It included 10 workshops, the Reconfig05 conference and a robotics Dec 9-11, 2009 ReConFig 09 Chair of Reconfigurable computing for Robotics track, with Dr. Eduardo Marques (UCP, Brazil), and steering committee member. IEEE International Conference on Reconfigurable Computing (ReConFig 2009) Cancun, Mexico Dec 15, 2010 ReConfig10 IEEE International Conference on Reconfigurable Computing (ReConFig 2009) Cancun, Mexico Miguel Octavio Arias Estrada, Ph.D. Page 15 of 18

16 13. PARTICIPATION IN CONFERENCES, INVITED TALKS AND OTHER ACTIVITIES CONFERENCE AND CONGRESS PARTICIPATION Conference Date Duration Place ELECTRO 90 Oct days Chihuahua, Chih. Mexico CIECE 92 May days University of Guanajuato. Guanajuato, Gto. Mexico IRIS'94 Jun days University of Toronto. Toronto, ON. Canada ALIFE IV Jun days MIT, Cambridge, MA. USA II Mexicans Studying Abroad Conference Feb days George Washington University, Washington, DC. USA IRIS 95 Jun days Vancouver, BC. Canada III Mexicans Studying Mar days MIT/Harvard, Cambridge, MA. USA Abroad Conference IRIS 96 Jun days Montreal, PQ. Canada ISATA 97 Jun days Florence, Italy CAMP 97 Oct days Boston, MA. USA AFPAEC 98 May days Zurich, Switzerland IRIS 98 Jun days Vancouver, BC. Canada TAINA Nov days Mexico city. Mexico ISTEC Nov days Porto Alegre, Brasil FPGA Feb days Monterey, CA. USA DLW Jul days University of New Mexico Albuquerque, NM. USA ENC' Sep days Pachuca, Hgo. Mexico Electronic Imaging Jan days San Jose, CA. USA (SPIE) FPL Aug days Villach, Austria CAMP' Sep days Padova, Italy Electronic Imaging Jan days San Jose, CA. USA (SPIE) AeroSense 2001 (SPIE) April days Orlando, FL. USA FPL Aug days Belfast, Ireland TAINA Nov days México, DF. FPL Sept days Montpellier, France Congreso Nac. de Vinculación para la competitividad may, days Foro Consultivo Científico y Tecnológico Querétaro, Queretaro FPL Sept days Lisboa, Portugal ENC Sept days Apizaco, Tlaxcala ICFPT Dec days Tokyo, Japan ReConFig Sep days Colima, Col. ENC Sep days Colima, Col. SLALP Nov days Sao Carlos, SP, Brasil READ June days Evry, France ENC Sep days Puebla, Pue Reconfig Sep days Puebla, Pue ARC Mar days Karlsruhe Institute of Technology, Germany SLP Apr days USP, Sao Carlos, Brazil ReConFig days Cancun,QR CONIELECOMP days Puebla, Pue SPL days Bento Gonçalves, Brasil ISUM days Guanajuato, Gto Attended Workshops Workshop Dates Period Place Introduction to Cadence 4.2 May 12-15, days Canadian Microelectronics Corporation Queen s University, Kingston, ON. Canada International CMOS camera Workshop Oct 17-18, days AT&T Bell Laboratories, Homdel, NJ. USA 1996 NSF Workshop on Neuromorphic Engineering Jun 24 Jul 14, weeks California Institute of Technology, The Salk Institute and the NSF. Telluride, CO. USA Xilinx Workshop Oct 19-20, days CINVESTAV, IPN. Mexico city. JPEG 2000 standard Jan 27-28, days San Jose, CA. USA Miguel Octavio Arias Estrada, Ph.D. Page 16 of 18

17 Invited Speaker in Conference / Academic Event Conference Date Event Round table participation: current trends in computing Oct 23, 1999 Conferencia en Computación, I.Tec. Apizaco, Tlaxcala, Tlax. FPGA Architectures for Computer Vision Nov 26, 1999 Taller de Computación: Robótica y Visión. ITESM. Cuernavaca, Morelos FPGA Architectures for Computer Vision FPGA based architectures for computer vision applications Cómputo reconfigurable aplicado a la visión por computadora Diseño Digital con FPGAs y su aplicación en Sistemas de visión por computadora Tecnología FPGA y sus aplicaciones a la visión por computadora Cómputo reconfigurable aplicado a la visión por computadora Visión por computadora usando FPGAs 6 Años de investigación en FPGA para la visión por computadora Coordinador de sesión Tecnología FPGAs para aplicaciones en robótica móvil FPGAs aplicados a robótica móvil Sistemas de Visión con FPGAs Cómputo de Alto desempeño con FPGAs y GPUs Alternativas de aceleración para algoritmos Aceleración de algoritmos con FPGAs y GPUs: tendencias actuales y futuras FPGAs para Procesamiento de Imágenes June 21, 2000 Faculty invitation for their graduate program FIMEE, U. de Gto. Salamanca, Gto. Feb 9, 2001 Conferencia Internacional en Cómputo Aplicado CICA 2001 Instituto Tecnológico de Tlaxcala. Tlaxcala, Tlax. 14 nov, º. Ciclo de conferencias Sistemas-Informática Inst. Tecnológico de Estudios Superiores de la Región Carbonífera. Sabinas, Coahuila May a. semana de ingeniería electrónica Inst. Tecnológico Superior de Irapuato 20 oct 2003 Universidad DeLaSalle Bajio Escuela de Ing. En Computación y Electrónica León, Guanajuato 30 jan 2004 Fac. De Ciencias de la Computación, BUAP Capítulo estudiantil ACM de la FCC 29 apr 2004 Universidad Cuauhtémoc Facultad de Sistemas Computacionales Puebla, Pue nov 2004 SLALP 2004 (Simposio Latino Americano en Aplicaciones de Lógica Programable y Procesadores Digitales de Señales en Procesamiento de Video, Visión computacional y Robótica) Escuela de Ing. Eléctrica de San Carlos USP Sao Carlos, SP, Brasil 24 abr º Congreso de Ingeniería en Computación. Universidad Autónoma de Tlaxcala Facultad de Ciencias Básicas, Ingeniería y Tecnología Calpulalpan, Tlaxcala 15 oct 2009 Plática invitada para evento de la maestría en sistemas computacionales del Instituto Tecnológico de Apizaco Apizaco, Tlaxcala 28 oct 2009 Plática invitada en CONCIBE 2009 Congreso de Computación, Informática, Biomédica y Electrónica. Guadalajara, Jal. 19 oct 2011 Plática invitada en 3er Congreso Nacional de Tecnología Computacional e Informática. Facultad de Estudios Superiores Acatlán, UNAM 14 nov 2011 Plática invitada en CONACYT 2011 Congreso Nacional de Ciencias de la Computación BUAP, Puebla 16 nov 2011 Plñatica invitada al Simposium de Ingeniería Eléctrica- Electrónica Instituto Tecnológico de Culiacán, Sinaloa 20 abr 2012 Conferencia magistral en el Taller de Sistemas Digitales Avanzados FPGA usando VHDL Miguel Octavio Arias Estrada, Ph.D. Page 17 of 18

18 Journal / Conference / Project Invited reviewer Journal Reviewer Date Notes Journal of Machine Vision Systems and to date Regular reviewer Applications International Journal of Reconfigurable Systems review, guest editor Journal of Systems Architecture, Elsevier 2009 to date Regular reviewer IEEE Industrial Electronics 2009 to date Regular reviewer Image and Vision Computing, Elsevier review Conference Reviewer IARIA - etelemed 2012 CIARP 2009 MICAI ReConFig Founder, Steering comittee member. Chair of FPGA for robotics track 2009 IberChip 2009 CONCIBE 2007 ENC CONIELECOMP 2004 Projects / Grants Reviewer Conacyt projects and sabbatical evaluation to date 4 to 6 projects per year Conacyt sabbatical evaluation University of Guanajuato projects Fomix- Fondos mixtos Guanajuato 2009 Fomix- Fondos mixtos Querétaro 2008 ITESM internal projects grants 2007, 2008 Conacyt 2005 BUAP 2003 Miguel Octavio Arias Estrada, Ph.D. Page 18 of 18