VERIFICACIÓN FÍSCA CON DIVA

Transcripción

1 SEMINARI DE DOCTORAT HERRAMIENTAS CAD DE DISEÑO MICROELECTRÓNICO I VERIFICACIÓN FÍSCA CON DIVA José Luis González Jiménez (Extraído del material del Hit-Kit de AMS) Departament d Enginyeria Electrònica Universitat Politècnica de Catalunya Herramientas CAD de Diseño Microelectrónico I. Verificación física 1 Flujos de diseño: Custom Cell Layout Design Flow Manually perform the cell layout using Virtuoso(XL) Perform a design rule check Do a flat Extraction without any switches. Run a transistor level LVS After successful LVS, extract the layout including parasitic capacitances using the switch capall, PRC or res as required. Resimulate the design using the extracted view. Perform a final DRC without selecting any switches. Herramientas CAD de Diseño Microelectrónico I. Verificación física 2

2 Flujos de diseño: Standard Cell Layout Design Flow Perform layout with Silicon Ensemble / Cell Ensemble or place Standard Cells with Virtuoso(XL). Import data from Silicon Ensemble into Cadence layout view Replace all views with "abstract_mlvs" view (if required) SE: Within Cadence/Virtuoso replace all views using: Edit -> Search -> Replace Perform a design rule check with no switches set. Do a macro cell extraction. Set "Macro Mode LVS" in the HIT-Kit Utilities menu. Run the Macro LVS. After layout with Silicon Ensemble or Cell Ensemble extract the parasitics for resimulation. After successful Macro LVS and if the layout view of standard cells is available continue with the following steps: Replace the "abstract_mlvs" view with the "layout" view Run a full DRC Do a flat extraction. UnSet the "Macro Mode LVS" in the HIT-Kit Utilities Menu. Run the final transistor level LVS. Herramientas CAD de Diseño Microelectrónico I. Verificación física 3 DRC: verificación de reglas de diseño Diva Design Rule Check for 0.35µm Technologies The rule file for DRC enables online checking during the design phase, automatic creation ofgenerated layers and performing final verification before tape-out. For final verification you should note that the standard family cells do not conform to the design rules. Examples of design rules: Herramientas CAD de Diseño Microelectrónico I. Verificación física 4

3 DRC: verificación de reglas de diseño Ejemplo de regla de estructura: POLY1 Herramientas CAD de Diseño Microelectrónico I. Verificación física 5 DRC: verificación de reglas de diseño Ejemplo de regla de elemento: CONT Herramientas CAD de Diseño Microelectrónico I. Verificación física 6

4 DRC: verificación de reglas de diseño Ejemplo de regla para la periferia: PAD Herramientas CAD de Diseño Microelectrónico I. Verificación física 7 DRC: verificación de reglas de diseño Uso de Diva DRC Diva DRC is invoked from a Virtuoso or VirtuosoXL window through the menu: Verify->DRC... Check, that the "Rules File" and "Rules Library" are correctly specified (Rules library must correspond to your design technology!). Herramientas CAD de Diseño Microelectrónico I. Verificación física 8

5 DRC: verificación de reglas de diseño Uso de Diva DRC If you want to set switches, then you have to push the "Set Switches" button, which will bring up another form where you can select between various switches: Herramientas CAD de Diseño Microelectrónico I. Verificación física 9 DRC: verificación de reglas de diseño Uso de Diva DRC DRC Switches: csxswitch This switch corrects metal notches, which may be produced by Silicon Ensemble. device_debug The flattening of symbolic contacts may create "dubious" polygons which can be ignored provided LVS is clean. This check is disabled by default. To check for these violations you must enable this check. grid It is recommended to use the grid of 0.1µm or 0.05µm but is not absolutely necessary. In the mask shop the layout snaps to a grid of 0.01µm. Normally grid violations are uncritical but these could cause systematic mismatch when offgrid geometries are used for high precision analog elements. no_coverage This switch can be used to disable the check for metal coverage. no_erc ERC is switched off (floating POLY1, floating POLY2, PSUB without TAP...) no_info Disables all checks that are only for informational purpose (not included in the Design Rule Document). no_recommendation Disables all checks that consider recommendations. reset_drc This switch should be used before a metal coverage check is made. This "check" produces a "0 error" DRC, which resets the used area of a design. Herramientas CAD de Diseño Microelectrónico I. Verificación física 10

6 DRC: verificación de reglas de diseño Uso de Diva DRC DRC Switches: csxswitch This switch corrects metal notches, which may be produced by Silicon Ensemble. device_debug The flattening of symbolic contacts may create "dubious" polygons which can be ignored provided LVS is clean. This check is disabled by default. To check for these violations you must enable this check. grid It is recommended to use the grid of 0.1µm or 0.05µm but is not absolutely necessary. In the mask shop the layout snaps to a grid of 0.01µm. Normally grid violations are uncritical but these could cause systematic mismatch when offgrid geometries are used for high precision analog elements. no_coverage This switch can be used to disable the check for metal coverage. no_erc ERC is switched off (floating POLY1, floating POLY2, PSUB without TAP...) no_info Disables all checks that are only for informational purpose (not included in the Design Rule Document). no_recommendation Disables all checks that consider recommendations. reset_drc This switch should be used before a metal coverage check is made. This "check" produces a "0 error" DRC, which resets the used area of a design. Herramientas CAD de Diseño Microelectrónico I. Verificación física 11 DRC: verificación de reglas de diseño Uso de Diva DRC Viewing DRC Errors After performing a DRC, reported DRC errors can be viewed either with Find Marker (menu: Verify->Markers->Find.. ) or with the DRC Error Viewer included in the HIT-Kit Utilities-menu: Herramientas CAD de Diseño Microelectrónico I. Verificación física 12

7 DRC: verificación de reglas de diseño Viewing DRC Errors Herramientas CAD de Diseño Microelectrónico I. Verificación física 13 Extract: extracción del circuito a partir del layout Layout Extraction Layout extraction must be performed prior to running LVS in order to extract all devices, it can also be used to extract parasitics for accurate postlayout simulation. There are two different extraction methods, either "flat" extraction, which can be used for transistor level LVS, or "macro cell" extraction, which can be used for gate or block level LVS. Diva extraction is invoked from a Virtuoso or VirtuosoXL window through the menu: Verify->Extract... To perform a transistor level extraction, the following options should be set: Herramientas CAD de Diseño Microelectrónico I. Verificación física 14

8 Extract: extracción del circuito a partir del layout Layout Extraction If you are going to perform a macro level LVS, then the form should look like this: Please check in both cases, that the Rules File and the Rules Library are correctly specified. If you want to set switches, then you have to push the "Set Switches" button, which will bring up another form where you can select between various switches: Herramientas CAD de Diseño Microelectrónico I. Verificación física 15 Extract: extracción del circuito a partir del layout Layout Extraction Extraction switches: capall This switch gives accurate extraction of layout parasitics with area and perimeter capacitances between each layer. This switch must not be used in conjunction with switch cap. Additionally for resistors (rpoly1, rpoly2,..) a parasitic model (rpoly1c, rpoly2c,..) is extracted taking care of parasitic substrate/well capacitances. For the technologies BYQ and BYR the device cpoly(b) is extracted as cpoly(b)3 taking care of parasitic resistors and capacitors. device_debug You will get an error message for each recognized device in the extracted design to be able to debug all devices easily. The DRC error viewer can be used to view the devices. Herramientas CAD de Diseño Microelectrónico I. Verificación física 16

9 Extract: extracción del circuito a partir del layout extraction with capall extraction without capall Herramientas CAD de Diseño Microelectrónico I. Verificación física 17 LVS: comparación entre esquemático y layout Diva LVS To perform LVS for analog designs you have to set the environment variable $CDS_Netlisting_Mode to "analog": setenv CDS_Netlisting_Mode Analog This allows parameter checking and backannotation into the schematic for resimulation. To make a transistor level LVS be sure that the Macro Mode LVS is unset. This can be done in the CIW window in the menu: HIT-Kit Utilities->LVS Utilities->UnSet Macro Mode LVS For a macro level LVS you have to set the Macro Mode LVS accordingly. This can be accomplished via the CIW window menu: HIT-Kit Utilities->LVS Utilities->Set Macro Mode LVS Herramientas CAD de Diseño Microelectrónico I. Verificación física 18

10 LVS: comparación entre esquemático y layout Diva LVS Diva LVS is invoked from a Virtuoso or VirtuosoXL window through the menu: Verify->LVS... The following form will appear: Please check, that the "Rules Library" and "Rules File" are set correctly. When you have entered all information in the form the LVS can be started by clicking on the "Run" button. Herramientas CAD de Diseño Microelectrónico I. Verificación física 19 LVS: comparación entre esquemático y layout Diva LVS Mecanismos de análisis de la comparación LVS: Herramientas CAD de Diseño Microelectrónico I. Verificación física 20

11 LVS: comparación entre esquemático y layout Diva LVS Mecanismos de análisis de la comparación LVS: Herramientas CAD de Diseño Microelectrónico I. Verificación física 21 LVS: comparación entre esquemático y layout Herramientas CAD de Diseño Microelectrónico I. Verificación física 22