Taller de Interrupciones

Transcripción

1 Taller de Interrupciones Organización del Computador I Carlos A. Di Pietro Departamento de Computación - FCEyN UBA 2 cuatrimestre 205

2 El PIC 6F84A El PIC6F84A es un microcontrolador de la empresa Microchip. Cuenta con las siguientes características: Característica Descripción Arquitectura Harvard Frecuencia de operación 20 MHz Memoria FLASH de programa 024 words Memoria de datos 68 Bytes Memoria de datos EEPROM 64 Bytes Interrupciones 4 Puertos de E/S 2 (A,B) Conjunto de Instrucciones 35

3 Introduccio n MPLabX Ejemplo Un poco sobre arquitecturas... Harvard von Neumann Misma memoria para las instrucciones y datos. Ma s lenta porque la memoria hace de cuello de botella. Requiere linea de control para multiplexar el bus (bus de control). Generalmente CISC. Memorias individuales para instrucciones y datos. Ma s ra pidas por acceso en paralelo a ambas memorias. El taman o de las instrucciones no esta relacionado con el de los datos. Generalmente RISC.

4 Encapsulado SSOP RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB RB2 RB PIC6F84A RA RA0 OSC/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4

5 Introducción ence Manual should be considered a complementary document to this data sheet, and is highly recommended device MPLabX functions. These functions include: Ejemplo reading for a better understanding of the External interrupt device architecture and operation of the peripheral Change on PORTB interrupt modules. Timer0 clock input El PIC The PIC6F84A belongs internamente to the mid-range family of the PICmicro microcontroller devices. A block diagram of the device is shown in Figure -. Table - details the pinout of the device with descriptions and details for each pin. FIGURE -: PIC6F84A BLOCK DIAGRAM FLASH Program Memory K x 4 3 Program Counter 8 Level Stack (3-bit) Data Bus RAM File Registers 68 x 8 8 EEPROM Data Memory EEDATA EEPROM Data Memory 64 x 8 Program Bus 4 Instruction Register 7 Addr Mux RAM Addr EEADR 5 Direct Addr 7 Indirect Addr TMR0 FSR reg 8 STATUS reg RA4/T0CKI Power-up Timer MUX 8 I/O Ports Instruction Decode & Control Oscillator Start-up Timer Power-on Reset ALU RA3:RA0 Timing Generation Watchdog Timer W reg RB7:RB RB0/INT OSC2/CLKOUT OSC/CLKIN MCLR VDD, VSS

6 Organización de la memoria En este PIC la memoria esta divida en: Memoria FLASH de programa. Memoria RAM de datos. Memoria EEPROM de datos.

7 Memoria de Programa RY ORGANIZATION emory blocks in the PIC6F84A. gram memory and the data memory. s own bus, so that access to each uring the same oscillator cycle. can further be broken down into the RAM and the Special Function. The operation of the SFRs that are described here. The SFRs used pheral modules are described in the each individual peripheral module. ry area also contains the data. This memory is not directly mapped ory, but is indirectly mapped. That is, s pointer specifies the address of the emory to read/write. The 64 bytes of memory have the address range ils on the EEPROM memory can be.0. tion on device memory may be found Mid-Range Reference Manual, FIGURE 2-: PC<2:0> CALL, RETURN 3 RETFIE, RETLW Stack Level Stack Level 8 User Memory Space PIC6F84A PROGRAM MEMORY MAP AND STACK - PIC6F84A RESET Vector Peripheral Interrupt Vector h 04h m Memory Organization s a 3-bit program counter capable K x 4 program memory space. For he first K x 4 (h-03ffh) are ented (Figure 2-). Accessing a locahysically implemented address will nd. For example, for locations 20h,, 020h, 420h, 820h, and C20h, 3FFh FFFh

8 Memoria de Datos PIC6F84A 2.2 Data Memory Organization The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 6 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 2-2 shows the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file ( F ), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 2.5). Indirect addressing uses the present value of the RP0 bit for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank. Each Bank extends up to 7Fh (28 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers, implemented as static RAM GENERAL PURPOSE REGISTER FILE Each General Purpose Register (GPR) is 8-bits wide and is accessed either directly or indirectly through the FSR (Section 2.5). The GPR addresses in Bank are mapped to addresses in Bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR. FIGURE 2-2: REGISTER FILE MAP - PIC6F84A File Address File Address h Indirect addr. () Indirect addr. () 80h 0h TMR0 OPTION_REG 8h 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 07h 87h 08h EEDATA EECON 88h 09h EEADR EECON2 () 89h 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch 8Ch 4Fh 50h 68 General Purpose Registers (SRAM) Mapped (accesses) in Bank 0 CFh D0h 7Fh FFh Bank 0 Bank Unimplemented data memory location, read as 0. Note : Not a physical register.

9 Selección de Bancos Para seleccionar el banco con el cual queremos trabajar tendremos que utilizar la directiva al ensamblador banksel junto con un registro perteneciente al banco al cual queremos acceder. Ejemplo: banksel NombreDelRegistro

10 Registro: W El registro de trabajo W (Working Register) es un registro de 8 bits que participa en la mayoría de las instrucciones. Es uno de los registro más importantes del microcontrolador. Puede ser accedido tanto para lectura como para escritura.

11 Furthermore, the TO and PD bits are not writable. instructions for examples. Introducción MPLabX Ejemplo Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Registro: STATUS For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 0u uuu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 7-2), because these instructions do not affect any status bit. REGISTER 2-: STATUS REGISTER (ADDRESS 03h, 83h) 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic R/W-0 R/W-0 R/W-0 R- R- R/W-x R/W-x R/W-x IRP RP RP0 TO PD Z DC C bit 7 bit 0 bit 7-6 Unimplemented: Maintain as 0 bit 5 RP0: Register Bank Select bits (used for direct addressing) 0 = Bank (80h - FFh) = Bank 0 (h - 7Fh) bit 4 TO: Time-out bit = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: A subtraction is executed by adding the two s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR = Bit is set 0 = Bit is cleared x = Bit is unknown DS357B-page 8 2 Microchip Technology Inc.

12 Puertos de Entrada/Salida Los PICs tienen la característica de que sus pines pueden ser todos configurados de acuerdo a la necesidad de la aplicación, es decir, que los pines de un mismo puerto pueden ser usados como entradas o como salidas. Los PIC 6F84A cuentan con dos puertos de E/S. Puerto A: Puerto bidireccional de 5 bits. Puerto B: Puerto bidireccional de 8 bits.

13 Registros TRIS Se utilizan para configurar los pines del PORTA y PORTB como Entradas o Salidas. Cada bit se corresponde con un pin del PORTA/PORTB Donde se escribe un el pin correspondiente sera entrada. Donde se escribe un 0 el pin correspondiente sera salida.

14 Set de instrucciones PIC6F84A TABLE 7-2: PIC6CXXX INSTRUCTION SET Mnemonic, Operands Description 4-Bit Opcode Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF Add W and f 0 dfff ffff C,DC,Z,2 ANDWF AND W with f dfff ffff Z,2 CLRF f Clear f 0 lfff ffff Z 2 CLRW - Clear W 0 0xxx xxxx Z COMF Complement f dfff ffff Z,2 DECF Decrement f dfff ffff Z,2 DECFSZ Decrement f, Skip if 0 (2) 0 dfff ffff,2,3 INCF Increment f dfff ffff Z,2 INCFSZ Increment f, Skip if 0 (2) dfff ffff,2,3 IORWF Inclusive OR W with f 0 dfff ffff Z,2 MOVF Move f 0 dfff ffff Z,2 MOVWF f Move W to f lfff ffff NOP - No Operation 0xx0 RLF Rotate Left f through Carry 0 dfff ffff C,2 RRF Rotate Right f through Carry dfff ffff C,2 SUBWF Subtract W from f 0 dfff ffff C,DC,Z,2 SWAPF Swap nibbles in f 0 dfff ffff,2 XORWF Exclusive OR W with f dfff ffff Z,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 0 bb bfff ffff,2 BSF f, b Bit Set f 0 0bb bfff ffff,2 BTFSC f, b Bit Test f, Skip if Clear (2) 0 0bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set (2) 0 bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W x kkkk kkkk C,DC,Z ANDLW k AND literal with W kkkk kkkk Z CALL k Call subroutine 2 0 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 0 TO,PD GOTO k Go to address 2 0 kkk kkkk kkkk IORLW k Inclusive OR literal with W 0 kkkk kkkk Z MOVLW k Move literal to W xx kkkk kkkk RETFIE - Return from interrupt 2 RETLW k Return with literal in W 2 0xx kkkk kkkk RETURN - Return from Subroutine 2 0 SLEEP - Go into standby mode TO,PD SUBLW k Subtract W from literal 0x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W kkkk kkkk Z Note : When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, ), the value used will be that value present on the pins themselves. For example, if the data latch is for a pin configured as input and is driven low by an external device, the data will be written back with a 0.

15 Configuración Inicial Macro de Inicialización config CP OFF & XT OSC & WDT OFF & PWRTE OFF OSC: Controla el modo de oscilación que usará el PIC para funcionar. WDT: (Watchdog Timer) Es una capacidad del microcontrolador de autorresetearse PWRTE: Permite generar un retardo en la inicialización del PIC. CP: Protección de código. Permite que el mismo no pueda ser leído por otra persona.

16 Declaración de constantes Podemos definir constantes usando la directiva al ensambaldor equ. Ejemplos: LED OFF equ 0xAB LED ON equ 0xCD Esta directiva realiza el remplazo sintáctico de la palabra a la izquierda del operador equ por la palabra ubicada del lado derecho del mismo.

17 Declaración de variables Del mismo modo, utilizando la directiva al ensambaldor equ, podemos declarar nombres de variables a las cuales accederemos utilizando un direccionamiento directo. Ejemplo: LED STATUS equ 0x20 ; declaracion de la variable movwf LED STATUS ; uso de la variable IMPORTANTE: Es necesario chequear cuales son las posiciones de memoria que tenemos disponibles para almacenar nuestras variables. Banco 0: 0x0C hasta 0x4F Banco : 0x8C hasta 0xCF

18 Interrupciones El PIC puede recibir una (y sólo una) interrupción a la vez. Al recibirla: Apila el PC (program counter) Deshabilita las interrupciones Pasa a ejecutar el código que se encuentre en el vector de interrupciones (que tiene una sola posición) ubicado en la posición 0x4

19 PIC6F84A Registro: INTCON INTCON REGISTER The INTCON register is a readable and writable register that contains the various enable bits for all interrupt sources. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE EEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit bit 0 GIE: Global Interrupt Enable bit = Enables all unmasked interrupts 0 = Disables all interrupts EEIE: EE Write Complete Interrupt Enable bit = Enables the EE Write Complete interrupts 0 = Disables the EE Write Complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR = Bit is set 0 = Bit is cleared x = Bit is unknown

20 2.3.2 OPTION REGISTER Registro: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. PIC6F84A Note: When the prescaler is assigned to the WDT (PSA = ), TMR0 has a : prescaler assignment. REGISTER 2-2: OPTION REGISTER (ADDRESS 8h) R/W- R/W- R/W- R/W- R/W- R/W- R/W- R/W- RBPU INTEDG T0CS T0SE PSA PS2 PS PS0 bit 7 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 RBPU: PORTB Pull-up Enable bit = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate : 2 : 4 : 8 : 6 : 32 : 64 : 28 : 256 : : 2 : 4 : 8 : 6 : 32 : 64 : 28 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR = Bit is set 0 = Bit is cleared x = Bit is unknown

21 PIC6F84A Introducción MPLabX Ejemplo Salvando los registros 6.9 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. The code in Example 6- stores and restores the STATUS and W register s values. The user defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values. Example 6- does the following: a) Stores the W register. b) Stores the STATUS register in STATUS_TEMP. c) Executes the Interrupt Service Routine code. d) Restores the STATUS (and bank select bit) register. e) Restores the W register. EXAMPLE 6-: SAVING STATUS AND W REGISTERS IN RAM PUSH MOVWF W_TEMP ; Copy W to TEMP register, SWAPF STATUS, W ; Swap status to be saved into W MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register ISR : : : ; Interrupt Service Routine : ; should configure Bank as required : ; POP SWAPF STATUS_TEMP,W ; Swap nibbles in STATUS_TEMP register ; and place result into W MOVWF STATUS ; Move W into STATUS register ; (sets bank to original state) SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMP SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W 6.0 Watchdog Timer (WDT) The Watchdog Timer is a free running On-Chip RC Oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC/CLKIN pin. That means that the WDT will run even if the clock on the OSC/CLKIN and OSC2/CLKOUT pins of the device has been 6.0. WDT PERIOD The WDT has a nominal time-out period of 8 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to :28 can be assigned to the WDT under software control by

22 MPLabX Descarga:

23 MPLabX - Primeros pasos Para crear un nuevo proyecto en la IDE debemos realizar los siguientes pasos: Create New Project Standalone Project Device: PIC6F84A Select Tool Next (Grabadora de PIC) Compiler: mpasm (Ensamblador) Asignar nombre y directorio Finish... Source Files Add Existing Item Probemoslo con ejemplo.asm...