NVIC : Nested Vectored Interrupt Controller

NVIC : Nested Vectored Interrupt Controller Laboratorio de Microprocesadores 03/09/2015 Laboratorio de Microprocesadores Ing. Daniel Jacoby1

NVIC Nested Vector Interrupt Controller La arquitectura Cortex M4 tiene un control avanzado de interrupciones y excepciones. El NVIC recibe excepciones del sistema así como interrupciones externas. MK64F12.h 03/09/2015 Laboratorio de Microprocesadores 2

NVIC Nested Vector Interrupt Controller ARM CORE System Exceptions 03/09/2015 Laboratorio de Microprocesadores 3

NVIC Nested Vector Interrupt Controller External Interrupts El NVIC puede aceptar hasta 240 Interrupciones externas La cantidad efectiva depende del fabricante. 03/09/2015 Laboratorio de Microprocesadores 4

NVIC Nested Vector Interrupt Controller K64F Core Interrupts 03/09/2015 Laboratorio de Microprocesadores 5

NVIC Nested Vector Interrupt Controller K64F External Interrupts 03/09/2015 Laboratorio de Microprocesadores 6

NVIC Nested Vector Interrupt Controller K64F External Interrupts (Ultimas) IRQn = Vector Nr -16 03/09/2015 Laboratorio de Microprocesadores 7

InterruptVector Numbers MK64FN1M0VLL12 MK64F12.h /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ 03/09/2015 Laboratorio de Microprocesadores 8

InterruptVector Numbers MK64FN1M0VLL12 MK64F12.h /* Device specific interrupts */ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ MCM_IRQn = 17, /**< Normal Interrupt */ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ RNG_IRQn = 23, /**< RNG Interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ 03/09/2015 Laboratorio de Microprocesadores 9

InterruptVector Numbers MK64FN1M0VLL12 MK64F12.h /* Device specific interrupts (cont) */ SPI0_IRQn = 26, /**< SPI0 Interrupt */ SPI1_IRQn = 27, /**< SPI1 Interrupt */ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ ADC0_IRQn = 39, /**< ADC0 interrupt */ CMP0_IRQn = 40, /**< CMP0 interrupt */ CMP1_IRQn = 41, /**< CMP1 interrupt */ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ CMT_IRQn = 45, /**< CMT interrupt */ RTC_IRQn = 46, /**< RTC interrupt */ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ PDB0_IRQn = 52, /**< PDB0 Interrupt */ USB0_IRQn = 53, /**< USB0 interrupt */ USBDCD_IRQn = 54, /**< USBDCD Interrupt */ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ 03/09/2015 Laboratorio de Microprocesadores 10

InterruptVector Numbers MK64FN1M0VLL12 MK64F12.h /* Device specific interrupts (cont) */ DAC0_IRQn = 56, /**< DAC0 interrupt */ MCG_IRQn = 57, /**< MCG Interrupt */ LPTMR0_IRQn = 58, /**< LPTimer interrupt */ PORTA_IRQn = 59, /**< Port A interrupt */ PORTB_IRQn = 60, /**< Port B interrupt */ PORTC_IRQn = 61, /**< Port C interrupt */ PORTD_IRQn = 62, /**< Port D interrupt */ PORTE_IRQn = 63, /**< Port E interrupt */ SWI_IRQn = 64, /**< Software interrupt */ SPI2_IRQn = 65, /**< SPI2 Interrupt */ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ CMP2_IRQn = 70, /**< CMP2 interrupt */ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ DAC1_IRQn = 72, /**< DAC1 interrupt */ ADC1_IRQn = 73, /**< ADC1 interrupt */ I2C2_IRQn = 74, /**< I2C2 interrupt */ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ SDHC_IRQn = 81, /**< SDHC interrupt */ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ } IRQn_Type; /* end of group Interrupt_vector_ numbers */ 03/09/2015 Laboratorio de Microprocesadores 11

InterruptVectors File: startup_mk64f12.s MK64FN1M0VLL12 Purpose: CMSIS Cortex-M4 Core Device Startup File Location: KDSWorkspace\Project_Name\Project_Settings\Startup_Code /* Core interrupts Vectors*/ _isr_vector:.long StackTop /* Top of Stack */.long Reset_Handler /* Reset Handler */.long NMI_Handler /* NMI Handler*/.long HardFault_Handler /* Hard Fault Handler*/.long MemManage_Handler /* MPU Fault Handler*/.long BusFault_Handler /* Bus Fault Handler*/.long UsageFault_Handler /* Usage Fault Handler*/.long 0 /* Reserved*/.long 0 /* Reserved*/.long 0 /* Reserved*/.long 0 /* Reserved*/.long SVC_Handler /* SVCall Handler*/.long DebugMon_Handler /* Debug Monitor Handler*/.long 0 /* Reserved*/.long PendSV_Handler /* PendSV Handler*/.long SysTick_Handler /* SysTick Handler*/ 03/09/2015 Laboratorio de Microprocesadores 12

File: startup_mk64f12.s InterruptVectors /* Device specific interrupts Vectors*/.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/.long DMA_Error_IRQHandler /* DMA Error Interrupt*/.long MCM_IRQHandler /* Normal Interrupt*/.long FTFE_IRQHandler /* FTFE Command complete interrupt*/.long Read_Collision_IRQHandler /* Read Collision Interrupt*/.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/.long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/.long WDOG_EWM_IRQHandler /* WDOG Interrupt*/.long RNG_IRQHandler /* RNG Interrupt*/.long I2C0_IRQHandler /* I2C0 interrupt*/.long I2C1_IRQHandler /* I2C1 interrupt*/.long SPI0_IRQHandler /* SPI0 Interrupt*/.long SPI1_IRQHandler /* SPI1 Interrupt*/.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ 03/09/2015 Laboratorio de Microprocesadores 13

File: startup_mk64f12.s InterruptVectors /* Device specific interrupts Vectors (cont)*/.long UART0_LON_IRQHandler /* UART0 LON interrupt*/.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/.long UART2_ERR_IRQHandler /* UART2 Error interrupt*/.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/.long UART3_ERR_IRQHandler /* UART3 Error interrupt*/.long ADC0_IRQHandler /* ADC0 interrupt*/.long CMP0_IRQHandler /* CMP0 interrupt*/.long CMP1_IRQHandler /* CMP1 interrupt*/.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/.long CMT_IRQHandler /* CMT interrupt*/.long RTC_IRQHandler /* RTC interrupt*/.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/.long PDB0_IRQHandler /* PDB0 Interrupt*/.long USB0_IRQHandler /* USB0 interrupt*/.long USBDCD_IRQHandler /* USBDCD Interrupt*/.long Reserved71_IRQHandler /* Reserved interrupt 71*/.long DAC0_IRQHandler /* DAC0 interrupt*/.long MCG_IRQHandler /* MCG Interrupt*/.long LPTMR0_IRQHandler /* LPTimer interrupt*/ 03/09/2015 Laboratorio de Microprocesadores 14

File: startup_mk64f12.s InterruptVectors /* Device specific interrupts Vectors (cont)*/.long PORTA_IRQHandler /* Port A interrupt*/.long PORTB_IRQHandler /* Port B interrupt*/.long PORTC_IRQHandler /* Port C interrupt*/.long PORTD_IRQHandler /* Port D interrupt*/.long PORTE_IRQHandler /* Port E interrupt*/.long SWI_IRQHandler /* Software interrupt*/.long SPI2_IRQHandler /* SPI2 Interrupt*/.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/.long UART4_ERR_IRQHandler /* UART4 Error interrupt*/.long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/.long UART5_ERR_IRQHandler /* UART5 Error interrupt*/.long CMP2_IRQHandler /* CMP2 interrupt*/.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/.long DAC1_IRQHandler /* DAC1 interrupt*/.long ADC1_IRQHandler /* ADC1 interrupt*/.long I2C2_IRQHandler /* I2C2 interrupt*/.long CAN0_ORed_Message_buffer_ IRQHandler /* CAN0 OR'd message buffers interrupt*/.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/.long SDHC_IRQHandler /* SDHC interrupt*/.long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/.long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/.long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/.long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/ 03/09/2015 Laboratorio de Microprocesadores 15

NVIC Nested Vector Interrupt Controller NVIC Registers 03/09/2015 Laboratorio de Microprocesadores 16

NVIC Nested Vector Interrupt Controller NVIC Registers 8X32=256 i.e.irq n=0-255 Ej: ISER[INT[IRQn/32]] 03/09/2015 Laboratorio de Microprocesadores 17

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_ISER0-NVIC_ISER7 03/09/2015 Laboratorio de Microprocesadores 18

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_ICER0-NVIC_ICER7 03/09/2015 Laboratorio de Microprocesadores 19

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_ISPR0-NVIC_ISPR7 03/09/2015 Laboratorio de Microprocesadores 20

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_ICPR0-NVIC_ICPR7 03/09/2015 Laboratorio de Microprocesadores 21

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_IABR0-NVIC_IABR7 03/09/2015 Laboratorio de Microprocesadores 22

NVIC Nested Vector Interrupt Controller NVIC Registers: NVIC_IPR0-NVIC_IPR59 03/09/2015 Laboratorio de Microprocesadores 23

NVIC Nested Vector Interrupt Controller K64F NVIC_IPR0-NVIC_IPR59 Una exception de mayor prioridad (nivel de prioridad mas bajo) puede interrumpir (preempt) a una excepción de menor prioridad (nivel de prioridad mas alto) La posicion del bit para el IPR es: 8 * (IRQn mod 4) + 4 03/09/2015 Laboratorio de Microprocesadores 24

NVIC Nested Vector Interrupt Controller IPR Numero de niveles Se han usado los bits mas significativos en lugar de los menos significativos para simplificar la migracion del software de un procesador a otro. Si los bits no implementados son los mas significativos se produce una inversion de la prioridad al portar de un procesador a otro. En el siguiente ejemplo podemos ver que al eliminar el MSB (b2) se invierte la prioridad bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IRQn / pri No Implementado 1 0 1 IRQ0 - No Implementado 0 1 1 IRQ1 + 03/09/2015 Laboratorio de Microprocesadores 25

NVIC Nested Vector Interrupt Controller Ej:Determinacion de la posicion del registro para un periferico (LPTMR Low Power Timer) Vector=74 IRQn=Vector-16=58 NVIC Non-IPR Register location = INT[IRQn/32]= INT[58/32]=1 NVIC IPR Register location = INT[IRQn/4]= INT[58/4]=14 Los registros involucrados son: ISER1, ICER1,ISPR1,ICPR1,IABR1,IP14 La posicion del bit para los Non IPR es: IRQn mod 32 = 58-32*1=26 03/09/2015 Laboratorio de Microprocesadores 26

NVIC Nested Vector Interrupt Controller Ej:Determinacion de la posicion del registro para un periferico (LPTMR Low Power Timer) La posicion del bit para el IPR es: 8 * (IRQn mod 4) + 4 = 8*(58 mod 4)+4 = 8*(58-14*4) +4=20 => IP14[23:20] IRQ59 IRQ58 IRQ57 IRQ56 IPR14 03/09/2015 Laboratorio de Microprocesadores 27

CMSIS Cortex Microcontroller Software Interface Standard 03/09/2015 Laboratorio de Microprocesadores 28

CMSIS Cortex Microcontroller Software Interface Standard Enable External Interrupt : The function enables a device-specific interrupt in the NVIC interrupt controller. Param [in]:irqn En core_cm4.h External interrupt number. Value cannot be negative. STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { INT[IRQn/32]] /* enable interrupt */ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)irqn) & (uint32_t)0x1f)); } Ejemplo: NVIC_EnableIRQ(PORTA_IRQn); IRQn mod 32 03/09/2015 Laboratorio de Microprocesadores 29

Ejemplo de interrupcion Ejemplo (cont) : ISR PORTA_IRQHandler (void) { // Clear port IRQ flag PORT_ClearInterruptFlag (PORTA, PIN);.. } PORTA_IRQn NVIC_EnableIRQ(PORTA_IRQn); PortA PIN void PORT_ClearInterruptFlag (PORT_t port, PORTBit_t bit) { port->pcr[bit] = PORT_PCR_ISF_MASK; } PORT_PCR_ISF_MASK =0x1000000u 03/09/2015 Laboratorio de Microprocesadores 30

SystickTimer El Systick timer es un contador descendente de 24 bits que esta integrado al NVIC y puede ser usado para generar una excepción (#15). En muchos sistemas operativos el timer es usado para administrar las tareas. Por ejemplo para permitir que múltiples tareas sean ejecutadas en diferentes momentos y evitar así que ninguna tarea bloquee al sistema. Estructura Interna 03/09/2015 Laboratorio de Microprocesadores 31

SystickTimer Control and Status Register Reload Value Register 03/09/2015 Laboratorio de Microprocesadores 32

SystickTimer Current Value Register Reload Value Register 03/09/2015 Laboratorio de Microprocesadores 33

SystickTimer El contador genera una interrupción cuando pasa de 1 a 0 y se recarga en el próximo flanco ascendente del clock. 04/09/2015 Laboratorio de Microprocesadores 34

SystickTimer Notas: Si se desea generar una interrupción periodicade N pulsos de clock el valor de recarga debe ser N -1!! Si se desea generar un retardo de N pulsos de clock el valor de inicial debe ser N!!. No es necesario borrar ningún flag al entrar a la interrupción del Systick dado que se trata de una excepción del propio core. 04/09/2015 Laboratorio de Microprocesadores 35

SystickTimer Secuencia de inicialización 1. Desabilitar el timer 0 Systick Status and control register 2. Escribir el nuevo valor en el Systick Reload Register 3. Escribir el Current Value register para ponerlo en 0 4. Escribir el Systick Status and control Register para arrancar el Systick void SysTick_Init (void) { SysTick->CTRL = 0x00; SysTick->LOAD = 12500000L - 1; // 125ms @ 100MHz SysTick->VAL = 0x00; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk SysTick_CTRL_TICKINT_Msk SysTick_CTRL_ENABLE_Msk; } _ISR SysTick_Handler (void) { // Your code Here } 03/09/2015 Laboratorio de Microprocesadores 36

END Interrupts 03/09/2015 Laboratorio de Microprocesadores 37