EE 361L Implementation Notes for Subproject 1

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1 EE 361L Implementation Notes for Subproject 1 You are to implement the pipelined MIPSL so that it can execute the instructions: add addi beq Assume the controller of the pipelined MIPSL works according to state diagram shown in Figure 1. Reset Instruction Fetch State 0 Insert Bubble PC = PC+2 Instruction Decode State 1 Stall PC State 2 Stall PC Insert Bubble Figure 1. Controller State State 3 Insert Bubble Stall PC or Possibly PC = Branch Target Address State 0, Instruction fetch During this state, the instruction is fetched in the instruction fetch stage: The processor will read in the instruction pointed to by the program counter (PC). Note that the instruction is always loaded into the IF/ID pipeline register, which is to be used in the next stage. The PC is incremented by 2. A bubble is sent into ID/EX pipeline register so that the datapath doesn t do anything downstream along the pipeline State 1, Instruction decode During this stage, the instruction is decoded in the instruction decode stage. Note that we have the instruction and its opcode in the IF/ID pipeline register. The opcode is an input into the Controller. Given the opcode value, the Controller will determine what is the current instruction and then set its outputs so that the datapath will execute that instruction. o These outputs are RegWrite, RegDst, ALU_Select, ALUSrc, MemRead, MemWrite, MemtoReg, and Branch. These output signals are sent to the ID/EX pipeline register. The PC is stalled, i.e., hold its value. State 2, Execute During this state, the instruction is being executed (e.g., by the ALU) in the execute stage. The controller has to

2 Stall the PC, just as in state 1, since we re still processing the current instruction. Insert a bubble into the ID/EX pipeline register, so that there are no other instruction in the pipeline. State 3, Memory access During this state, the instruction is in the memory access stage. In this stage, the instruction will access memory. In addition, if the instruction is a conditional branch, and in particular beq, then the branch target address is loaded into the PC. The controller has to Update PC o If Branch = 1 and Zero = 1 then PC = Branch Target Address o Else PC is stalled Insert a bubble into the ID/EX pipeline register, so that there are no other instruction in the pipeline That completes the description of the four states of the controller. Note that in the pipelined MIPS, there is a stage 5, which is the write back stage. Note that we have not considered this stage in four states of the controller. However, we do not need an additional state 4 for the write back stage because the register file is triggered on a negative clock edge. Thus, the register file is written back between state 3 ( memory access ) and state 0 (the next instruction fetch ). Figure 2 is an example of the timing involved with the four states of the controller. Instruction fetch IF/ID = instr ID/EX = bubble PC = PC + 2 ID/EX = control PC stall EX/MEM = control ID/EX = bubble PC stall MEM/WB = control PC = target branch address (possibly) else PC stall ID/EX = bubble State 0 State 1 Instr decode State 2 Execute stage Figure 2. Timing example. State 3 Memory access and possibly branch State 0 Instruction fetch of next instruction Register write in the middle of the clock period

3 The following table shows the timing agan. Table 1. Timing of states. State 0 State 1 State 2 State 3 State 0 PC PC = PC + 2 PC stall (hold) PC stall PC = branch if PC = PC + 2 branch and zero = 1 Else PC stall ID/EX Bubble Control Bubble Bubble Bubble IF/ID instr ID/EX instr EX/MEM instr MEM/WB instr write back You are to complete the MIPSL pipelined processer so that it can run the program in IM1New.V. Recall that it multiplies 3 by 5. Address Instruction 0 L0: addi $2,$0,3 # Initialize $2 with 3. $2 is used as a counter 2 add $4,$0,$0 # Clear $4. $4 will be used to compute the product 4 L1: beq $2,$0,L0 # This loop will keep adding 5 to register $4 until counter $2 is 0 6 addi $4,$4,5 8 addi $2,$2, 1 # Decrement the counter 10 beq $0,$0,L1 Your PMIPSL0 should run with test bench file testbenchsub1.v. Note that your project should have testbenchsub1.v the testbench MIPS Parts.V parts of the MIPSL processor Control.V controller PMPLS0.V MIPSL processor IM1New.V the program that calculates 3 x 5 You can find the testbenchsub1.v and IM1New.V files in the same folder as the current document. In Appendix A there is a trace from a simulation run using an old simulator called veriwell. Also, the PMIPSL0 is different because the instruction set was different. But take a look and see what a simulation run looks like Hints You are allowed to make changes to the datapath and controller, as long as the basic datapath structure of five pipeline stages is preserved. These stages are instruction fetch, instruction decode, execute, memory access, and write back.

4 Hint 1: Rather than have a simple register for the PC counter, use a register that has more functions. In particular, it can have the following functions: PC = 0, for reset PC stall, which is a hold PC = Target branch address PC = PC+2 This circuit is a sequential circuit. It can be implemented with a 2 bit select, which is controlled by the controller. We will refer to this circuit as the PC logic. Your PC logic doesn t have to be like this, but this should give you an idea anyway. For example, the select can be different than a 2 bit select. It may be useful to have a different select to implement reset. Hint 2: The controller will have inputs from opcode field of IF/ID and the zero bit from EX/MEM. It may have other inputs too. It s outputs are control signals to the ID/EX register and the 2 bit select to the PC logic. Hint 3: Recall that a bubble into ID/EX implies that the controls for any write enables should be zero. Hint 4: Note that the controller that you are given may have problems. But it ll give you an idea of what to do. Remember that it is basically a 2 bit counter that continually goes through states 0, 1, 2, 3, 0,... It s outputs depend on its inputs and current state. Hint 5: Your processor should have a reset input. This will clear the PC and clear the controller to state 0.

5 Hint 6: When testbenching your circuit, you will likely want to displays signals within your circuit. For example, consider the following testbench of the circuit called CircuitX. module textbench; reg a,b,c; reg clock; wire y; initial clock = 0; always #1 clock = ~clock; CircuitX c1(y, clock, a, b, c); intial begin a= 0; b = 0; c = 0; # 4 a = 1; #2 b = 1; # 2 c = 1; # 2 $stop; end initial $monitor( a=%d, b=%d, c=%d, y=%d clock=%d\n,a,b,c,y,clock); endmodule If there is a bug in CircuitX you cannot display signals within the circuit. Next is a simple (but crude) method to display signals within the circuit. Modify the CircuitX module by adding an output. Then the output is attached to signals within the circuit module. module CircuitX(y, clock, a, b, c, probe)... the input and output declarations as before output [3:0] probe; assign probe[3:2] = signal 1; assign probe[1:0] = signal 2;... the rest of the module endmodule

6 The testbench will be modified below. module textbench; reg a,b,c; reg clock; wire y; wire [3:0] probe; initial clock = 0; always #1 clock = ~clock; CircuitX c1(y, clock, a, b, c, probe); intial begin a= 0; b = 0; c = 0; # 4 a = 1; #2 b = 1; # 2 c = 1; # 2 $stop; end initial $monitor( a=%d, b=%d, c=%d, y=%d clock=%d\n, signal1=%d, signal2=%d,a,b,c,y,clock,probe[3:2],probe[1:0]); endmodule Hint 7: Note that $time is a variable that equals the current time of the simulation. This can be a useful value to display.

7 Appendix A Example trace The following is output of veriwell when running the testbench. C1>. IMem(PC,Instr),ALU(Output), Dmem(Addr) [Clock,Reset] PC( x, ) ALU( x) Dmem( x) [0,1] Reset PC( 0, ) ALU( x) Dmem( x) [1,1] L0: addi $2,$0,3 PC( 0, ) ALU( x) Dmem( x) [0,0] PC( 2, ) ALU( 0) Dmem( x) [1,0] PC( 2, ) ALU( 0) Dmem( x) [0,0] PC( 2, ) ALU( 3) Dmem( 0) [1,0] PC( 2, ) ALU( 3) Dmem( 0) [0,0] PC( 2, ) ALU( 0) Dmem( 3) [1,0] PC( 2, ) ALU( 0) Dmem( 3) [0,0] PC( 2, ) ALU( 0) Dmem( 0) [1,0] add $4,$0,$0 PC( 2, ) ALU( 0) Dmem( 0) [0,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] PC( 4, ) ALU( 3) Dmem( 0) [1,0] PC( 4, ) ALU( 3) Dmem( 0) [0,0] PC( 4, ) ALU( 3) Dmem( 3) [1,0] L1: beq $2,$0,L0 PC( 4, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 3) Dmem( 3) [1,0] PC( 6, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 3) Dmem( 3) [1,0] PC( 6, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 0) Dmem( 3) [1,0] PC( 6, ) ALU( 0) Dmem( 3) [0,0] PC( 6, ) ALU( 0) Dmem( 0) [1,0] addi $4,$4,5 PC( 8, ) ALU( 0) Dmem( 0) [1,0] PC( 8, ) ALU( 0) Dmem( 0) [0,0] PC( 8, ) ALU( 5) Dmem( 0) [1,0] product being updated PC( 8, ) ALU( 5) Dmem( 0) [0,0] PC( 8, ) ALU( 6) Dmem( 5) [1,0] PC( 8, ) ALU( 6) Dmem( 5) [0,0] PC( 8, ) ALU( 6) Dmem( 6) [1,0] addi $2,$2, 1 PC( 8, ) ALU( 6) Dmem( 6) [0,0] PC( 10, ) ALU( 6) Dmem( 6) [1,0] PC( 10, ) ALU( 6) Dmem( 6) [0,0] PC( 10, ) ALU( 2) Dmem( 6) [1,0] PC( 10, ) ALU( 2) Dmem( 6) [0,0]

8 PC( 10, ) ALU( 0) Dmem( 2) [1,0] PC( 10, ) ALU( 0) Dmem( 2) [0,0] PC( 10, ) ALU( 0) Dmem( 0) [1,0] beq $0,$0,L1 PC( 10, ) ALU( 0) Dmem( 0) [0,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] L1: beq $2,$0,L0 PC( 6, ) ALU( 0) Dmem( 0) [1,0] PC( 6, ) ALU( 2) Dmem( 0) [1,0] PC( 6, ) ALU( 2) Dmem( 0) [0,0] PC( 6, ) ALU( 10) Dmem( 2) [1,0] PC( 6, ) ALU( 10) Dmem( 2) [0,0] PC( 6, ) ALU( 10) Dmem( 10) [1,0] addi $4,$4,5 PC( 6, ) ALU( 10) Dmem( 10) [0,0] PC( 8, ) ALU( 10) Dmem( 10) [1,0] PC( 8, ) ALU( 10) Dmem( 10) [0,0] PC( 8, ) ALU( 10) Dmem( 10) [1,0] product being updated PC( 8, ) ALU( 10) Dmem( 10) [0,0] PC( 8, ) ALU( 4) Dmem( 10) [1,0] PC( 8, ) ALU( 4) Dmem( 10) [0,0] PC( 8, ) ALU( 4) Dmem( 4) [1,0] addi $4,$4, 1 PC( 8, ) ALU( 4) Dmem( 4) [0,0] PC( 10, ) ALU( 4) Dmem( 4) [1,0] PC( 10, ) ALU( 4) Dmem( 4) [0,0] PC( 10, ) ALU( 1) Dmem( 4) [1,0] PC( 10, ) ALU( 1) Dmem( 4) [0,0] PC( 10, ) ALU( 0) Dmem( 1) [1,0] PC( 10, ) ALU( 0) Dmem( 1) [0,0] PC( 10, ) ALU( 0) Dmem( 0) [1,0] beq $0,$0,L1 PC( 10, ) ALU( 0) Dmem( 0) [0,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] L1: beq $2,$0,L0 PC( 6, ) ALU( 0) Dmem( 0) [1,0] PC( 6, ) ALU( 1) Dmem( 0) [1,0] PC( 6, ) ALU( 1) Dmem( 0) [0,0]

9 PC( 6, ) ALU( 20) Dmem( 1) [1,0] PC( 6, ) ALU( 20) Dmem( 1) [0,0] PC( 6, ) ALU( 20) Dmem( 20) [1,0] addi $4,$4,5 PC( 6, ) ALU( 20) Dmem( 20) [0,0] PC( 8, ) ALU( 20) Dmem( 20) [1,0] PC( 8, ) ALU( 20) Dmem( 20) [0,0] PC( 8, ) ALU( 15) Dmem( 20) [1,0] product being updated PC( 8, ) ALU( 15) Dmem( 20) [0,0] PC( 8, ) ALU( 2) Dmem( 15) [1,0] PC( 8, ) ALU( 2) Dmem( 15) [0,0] PC( 8, ) ALU( 2) Dmem( 2) [1,0] addi $2,$2, 1 PC( 8, ) ALU( 2) Dmem( 2) [0,0] PC( 10, ) ALU( 2) Dmem( 2) [1,0] PC( 10, ) ALU( 2) Dmem( 2) [0,0] PC( 10, ) ALU( 0) Dmem( 2) [1,0] PC( 10, ) ALU( 0) Dmem( 2) [0,0] PC( 10, ) ALU( 0) Dmem( 0) [1,0] PC( 10, ) ALU( 0) Dmem( 0) [0,0] PC( 10, ) ALU( 0) Dmem( 0) [1,0] beq $0,$0,L1 PC( 10, ) ALU( 0) Dmem( 0) [0,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] L1: beq $2,$0,L0 PC( 6, ) ALU( 0) Dmem( 0) [1,0] PC( 6, ) ALU( 0) Dmem( 0) [1,0] PC( 6, ) ALU( 30) Dmem( 0) [1,0] PC( 6, ) ALU( 30) Dmem( 0) [0,0] PC( 0, ) ALU( 30) Dmem( 30) [1,0] L0: addi $2,$0,3 PC( 0, ) ALU( 30) Dmem( 30) [0,0] PC( 2, ) ALU( 30) Dmem( 30) [1,0] PC( 2, ) ALU( 30) Dmem( 30) [0,0] PC( 2, ) ALU( 3) Dmem( 30) [1,0] PC( 2, ) ALU( 3) Dmem( 30) [0,0] PC( 2, ) ALU( 0) Dmem( 3) [1,0] PC( 2, ) ALU( 0) Dmem( 3) [0,0] add $3,$0,$0 PC( 2, ) ALU( 0) Dmem( 0) [1,0] PC( 2, ) ALU( 0) Dmem( 0) [0,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0] PC( 4, ) ALU( 0) Dmem( 0) [1,0]

10 PC( 4, ) ALU( 3) Dmem( 0) [1,0] PC( 4, ) ALU( 3) Dmem( 0) [0,0] PC( 4, ) ALU( 3) Dmem( 3) [1,0] L1: beq $2,$0,L0 PC( 4, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 3) Dmem( 3) [1,0] PC( 6, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 3) Dmem( 3) [1,0] PC( 6, ) ALU( 3) Dmem( 3) [0,0] PC( 6, ) ALU( 0) Dmem( 3) [1,0] PC( 6, ) ALU( 0) Dmem( 3) [0,0] PC( 6, ) ALU( 0) Dmem( 0) [1,0] addi $4,$4,5 PC( 8, ) ALU( 0) Dmem( 0) [1,0] PC( 8, ) ALU( 0) Dmem( 0) [0,0] PC( 8, ) ALU( 5) Dmem( 0) [1,0] product being updated PC( 8, ) ALU( 5) Dmem( 0) [0,0] PC( 8, ) ALU( 6) Dmem( 5) [1,0] Stop at simulation time 152 C1>