Mic-1: Microarchitecture. IJVM Instructions NOP. Computer Architecture WS January 2006 B+1. University of Fribourg, Switzerland

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Mic-1: Microarchitecture IJVM Instructions The instruction opcode is 8 bit wide University of Fribourg, Switzerland System I: Introduction to Computer Architecture WS 2005-2006 25.

1 Mic-1: Microarchitecture IJVM Instructions The instruction opcode is 8 bit wide University of Fribourg, Switzerland System I: Introduction to Computer Architecture WS January 2006 Offsets are 16 bits wide (stored in two consecutive bytes) For IINC varnum and const are each 8 bits wide (cannot use WIDE) Variable references are 8 bit wide (or 2 * 8 bits if the instruction is prefixed with WIDE) amos.brocco@unifr.ch Constant references are 2 byte wide <Computer Architecture WS , 18 January 2006> (1) <Computer Architecture WS , 18 January 2006> (2) PC=PC+1; ; goto(mr) NOP goto <Computer Architecture WS , 18 January 2006> (3) <Computer Architecture WS , 18 January 2006> (4)

2 read IADD 1 MDR = TOS = MDR + H; wr; goto IADD 2 MDR = TOS = MDR + H; wr; goto -1 iadd2 iadd3 <Computer Architecture WS , 18 January 2006> (5) <Computer Architecture WS , 18 January 2006> (6) IADD 3 ISU 1 write read MDR = TOS = MDR + H; wr; goto MDR = TOS = MDR H; wr; goto A+ -1 isub2 <Computer Architecture WS , 18 January 2006> (7) <Computer Architecture WS , 18 January 2006> (8)

3 ISU 2 MDR = TOS = MDR H; wr; goto write ISU 3 MDR = TOS = MDR H; wr; goto isub3 -A <Computer Architecture WS , 18 January 2006> (9) <Computer Architecture WS , 18 January 2006> (10) read IAND 1 MDR = TOS=MDR AND H; wr; goto IAND 2 MDR = TOS=MDR AND H; wr; goto -1 iand2 iand3 <Computer Architecture WS , 18 January 2006> (11) <Computer Architecture WS , 18 January 2006> (12)

4 IAND 3 IOR 1 write read MDR = TOS=MDR AND H; wr; goto MDR = TOS =MDR OR H; wr; goto Aand -1 ior2 <Computer Architecture WS , 18 January 2006> (13) <Computer Architecture WS , 18 January 2006> (14) IOR 2 MDR = TOS =MDR OR H; wr; goto write IOR 3 MDR = TOS =MDR OR H; wr; goto ior3 Aor <Computer Architecture WS , 18 January 2006> (15) <Computer Architecture WS , 18 January 2006> (16)

5 DUP 1 DUP 2 write MDR = TOS; wr; goto MDR = TOS; wr; goto +1 dup2 <Computer Architecture WS , 18 January 2006> (17) <Computer Architecture WS , 18 January 2006> (18) read POP 1 MAR = SP = SP 1; rd (no operation) TOS = MDR; goto POP 2 MAR = SP = SP 1; rd (no operation) TOS = MDR; goto -1 pop2 0 pop3 <Computer Architecture WS , 18 January 2006> (19) <Computer Architecture WS , 18 January 2006> (20)

6 POP 3 ILOAD 1 MAR = SP = SP 1; rd (no operation) TOS = MDR; goto H = LV MAR = MRU + H; rd ; write; TOS = MDR; goto iload2 <Computer Architecture WS , 18 January 2006> (21) <Computer Architecture WS , 18 January 2006> (22) read ILOAD 2 H = LV MAR = MRU + H; rd ; write; TOS = MDR; goto ILOAD 3 H = LV MAR = MRU + H; rd ; write; TOS = MDR; goto A+ iload3 +1 iload4 <Computer Architecture WS , 18 January 2006> (23) <Computer Architecture WS , 18 January 2006> (24)

7 , write ILOAD 4 H = LV MAR = MRU + H; rd ; write; TOS = MDR; goto ILOAD 5 H = LV MAR = MRU + H; rd ; write; TOS = MDR; goto +1 iload5 <Computer Architecture WS , 18 January 2006> (25) <Computer Architecture WS , 18 January 2006> (26) GOTO 1 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto GOTO 2 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto MR= GOTO PC MR= OFFSET 1 PC GOTO OFFSET 1OFFSET 2 GOTO OFFSET 1OFFSET 2-1 goto2 +1 goto3 <Computer Architecture WS , 18 January 2006> (27) <Computer Architecture WS , 18 January 2006> (28)

8 GOTO 3 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto H= OFFSET MR= 0 OFFSET 1 PC GOTO 4 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto H= OFFSET 1 OFFSET 2 MR= OFFSET 2 PC GOTO OFFSET 1OFFSET 2 GOTO OFFSET 1OFFSET 2 goto4 Aor goto5 << 8 <Computer Architecture WS , 18 January 2006> (29) <Computer Architecture WS , 18 January 2006> (30) GOTO 5 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto GOTO 6 OPC = PC 1 H = MR << 8 H = MRU OR H PC = OPC + H; goto H= OFFSET 1 OFFSET 2 MR= OFFSET 2 PC GOTO OFFSET 1OFFSET 2... addr(goto)+ OFFSET A+ goto6 <Computer Architecture WS , 18 January 2006> (31) <Computer Architecture WS , 18 January 2006> (32)

9 IFEQ 1 IFEQ 2 read MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F -1 ifeq2 ifeq3 <Computer Architecture WS , 18 January 2006> (33) <Computer Architecture WS , 18 January 2006> (34) IFEQ 3 IFEQ 4 MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F Highit = JAMZ AND Z MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F If F starts at microaddress 0x092 then T starts at microaddress 0x192 (Highit = 1) The Highit is set depending on the value of Z =1 ifeq4 0/1 F 001 The value traversing the ALU sets Z <Computer Architecture WS , 18 January 2006> (35) <Computer Architecture WS , 18 January 2006> (36)

10 T F 1 OPC = PC 1; goto goto2; PC = PC + 1 goto In OPC the address of the conditional test (IFEQ, IF_ICMPEQ,...) is saved Continue as with GOTO, to determine the target jump offset -1 goto2 +1 F2 <Computer Architecture WS , 18 January 2006> (37) <Computer Architecture WS , 18 January 2006> (38) F 2 PC = PC + 1 goto F 3 PC = PC + 1 goto +1 F3 <Computer Architecture WS , 18 January 2006> (39) <Computer Architecture WS , 18 January 2006> (40)

11 WIDE WIDE_ISTORE 1 PC=PC+1;;goto(MR or 0x100) As variables are referenced with their offset from the LV pointer, to access variables stored at an offset bigger than 256 bytes the WIDE prefix is to be called before the ILOAD or ISTORE instruction (which normally take 8 bit offsets). WIDE make possible to use 16 bit offsets in the following instruction. H = MRU << 8 H = MRU OR H MAR = LV + H; goto istore3 MR contains the opcode of the next instruction (ILOAD or ISTORE). The wide version of ILOAD and ISTORE are located at: WIDE_ILOAD is at (addr of ILOAD) OR 0x100 WIDE_ISTORE is at (addr of ISTORE) OR 0x x wide_istore2 <Computer Architecture WS , 18 January 2006> (41) <Computer Architecture WS , 18 January 2006> (42) WIDE_ISTORE 2 WIDE_ISTORE 3 H = MRU << 8 H = MRU OR H MAR = LV + H; goto istore3 H = MRU << 8 H = MRU OR H MAR = LV + H; goto istore3 wide_istore3 Aor wide_istore4 << 8 <Computer Architecture WS , 18 January 2006> (43) <Computer Architecture WS , 18 January 2006> (44)

12 WIDE_ISTORE 4 H = MRU << 8 H = MRU OR H MAR = LV + H; goto istore3 A+ istore3 <Computer Architecture WS , 18 January 2006> (45)

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