Bandwidth requirements for communication systems based on. their low cost, low power consumption and inherent small silicon

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1 ELECTRÓNICA Ingeniería Electrónica, Automática y Comunicaciones, ol. XXI, No. -3, 5 Two MOS transimpedance amplifier on-chip structures for high-frequency applications. Martínez, A. Díaz, A. Torres, R. S. Murphy 3 and. L. Finol 3 Universidad Cristobal Colón, Departamento de Posgrado, eracruz, México. Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla, México. 3 Motorola, SPS. Chandler, AZ854, USA. RESUMEN / ABSTRACT Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM33, modified BSIM3v3, and EK models for high-frequency applications. Experimental and simulation results were performed for a.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from S-parameters, show a transimpedance gain of 4 db and a bandwidth of GHz. Key words: analog amplifiers, broadband amplifiers, BiCMOS integrated circuits, optical communication, optical receiver. En este trabajo se describe un sistema de recepción opto-electrónico, completamente con tecnología MOS. La retroalimentación negativa local es utilizada en el transistor de entrada para incrementar el ancho de banda y reducir el nivel de ruido. Se comparan los resultados simulados y experimentales del prototipo, utilizando los modelos BSIM33, BSIM33 modificado y EK, que demuestran el funcionamiento del sistema propuesto basado en a mediciones de parámetros S, Y y Z. Palabras clave: amplificadores analógicos, amplificadores de banda ancha, circuitos integrados BiCMOS, comunicación óptica, receptor óptico Recibido: octubre 5 Aprobado: noviembre 5 INTRODUCTION Bandwidth requirements for communication systems based on fiber optic receiver have recently increased their range from to 5 GHz. In that operation range, all intrinsic and extrinsic parasitic effects of MOS transistors must be included.,3 Several input stages for fiber optic receivers based on bipolar transistors have been reported in recent literature to overcome that loading effect. 4,5,6 Some of these implementations have used the shuntseries feedback over several common-emitter stages to increase the TIA bandwidth. 4,5 However, these implementations exhibit peaks in their frequency response, affecting the reception process. The common-base TIA has presented a better behavior than common-emitter implementations. 7 Since input stages have stringent requirements, such as high gain, low noise figure and wide bandwidth, its design is one of the most important issues in fiber optic communication systems. Despite MOS transistors amplifiers have inherently poor performance at high frequencies, their low cost, low power consumption and inherent small silicon area have motivated some research nowadays. 8,9 Several fully MOS implementations, using common-gate and regulated cascode implementations, have been recently reported. 8,9 The present work describes two fully CMOS TIA topologies for fiber optic applications, using an integrated photodiode to minimize parasitic effects due to interconnections. Negative feedback is used at the input transistor to increase the bandwidth and reduce the noise levels. The OEIC circuit design section presents the theoretical considerations of the photodiode and

2 Ingeniería Electrónica, Automática y Comunicaciones, /5 TIA structures, as well as the effect of that feedback in the preamplifier characteristics and the effect of the MOS transistor in high-frequency application. The experimental and simulated results, are described and finally the conclusion are presented. OEIC CIRCUIT DESIGN The structure of the photodiode used as receiver is presented in the figure. Since the chosen technology does not has epitaxial layers, the photodiode is a planar diffused pn junction; therefore the optical response is located in the visible range. The photo current generated, is, is given by: L ( W) 5* S( W )...() R: As the responsivity. G: As the generation factor. p(t): As incident light power. The photodiode capacitance C is defined by: c c s + c gs : Amplifier input capacitance. c gs : Transistor M gate-source capacitance. The output capacitance can be defined as: c c gd + c db + c p c gd and c db : Are the gate-drain and drain-bulk capacitances of transistor M. c p : Coupling capacitance to the next stage. The transfer function in equation (4) has two real poles at: S PG ; S F I G...(5) Since r ds is large, we can assume that g ds << g m. On the other hand, c in c the input capacitance of M, and the input impedance is given by: F ª H H R $ ' R «EL D» T $ ' ¼ H H & $ () L P...(6) and the photodiode resistance is giving by: G9 QN7 5G 5 G, T,...(3) I From equation (5) the 3 db cutoff frequency is obtained as: 3dB P S( F F )...(7) and when s the expression (4) the gain of the amplifier is given by: Y L R # 5 I...(8) 9 '' 5 I Figure Proposed photodiode fabricated with area X µm. Y R The preamplifier described in figure has a common-gate configuration, with an input capacitive coupling. 9 Its transfer function is given by the expression:,eldã L F 9ELDÃ,ELDÃ F / YR P G L F F ª F ( ) F ( ) ( ) G P I G ¼ I G P... (4) Figure Common-gate TIA amplifier for OEIC systems

3 Two MOS Transimpedance... A bandwidth increasing can be achieved by using a local feedback network, as shown in figure 3, 9 where the feedback network stage an inductor affect. That structure shows an increasing in the dominant pole frequency, due to the negative feedback, which is given by: S P F F (. ) K g m R bias...(9) The negative feedback also reduces the total noise of the circuit, which is now given by the equation: L ½ ª F F..F G ¼ LF ¾ ( P..FG ) ª F F. P. L ¼ 5I int 9 '' 5 I,ELDÃ,ELDÃ L F,ELDÃ F / () Figure 3 Modified common-gate structure TIA applications in OEIC systems. In high-frequency applications, S-parameters are use to obtain a better representation of the TIA structures, and are described by: ª ( 6 )( 6 ) 66 ( 6 )( 6 ) 6 6 ¼ ª ( 6 )( 6 ) 6 6 ( 6)( 6) 6 6 ¼ ª 6 ( 6 )( 6 ) 6 6 ¼ Y R...()...()...(3) 5 Z : Input impedance. Z : Output impedance. Z : Transfer function of the TIA structures. Transfer Y-parameter, based on the Z, is defined by: < < < < < MEASUREMENT...(4) TIA structures were simulated using BiCMOS level 49 model in HSPICE and Spectre, using the BSIM3v3 and modified BSIM3v3,,3 and level 53 model in HSPICE using EK model. In the modified BSIM3v3 model, resistance effects in the gate, source, and drain were added in the input transistor of both structures. In figure 4, the S-parameters of high-frequency response from MHz to 5 GHz are shown. In figure 4, Smith-Chart of the common-gate TIA impedance, based in S-parameters, presents high-frequency-capacitive effects. The Smith-Chart of the modified common-gate TIA is presented in the figure 4, where inductor and capacitive effects in frequency response it can be noticed. A transimpedance gain of 4 db was obtained using an R f of Ω, and a,3 pf output capacitance. From simulations, using a BSIM3v3 model, a photodiode capacitance of pf was estimated. Experimental results of the gain and bandwidth of common-gate TIA are shown in the figure 5. The transimpedance gain was calculated from the measured S-parameters using the following formula: YRXW 6 5 L 6 :...(5) A microphotography of the common-gate TIA die is shown in figure 6, while the OEIC chip is shown in figure 7, both fabricated using an AMS,8 µm BiCMOS process. Two-port on-wafer S-parameters were measured connecting the un-used input and output ports to 5-Ω impedances. Measurements were realized using a Wiltron vector-analyzer, model 36, and a Tektronics S-parameters test model 576. Transforming S-parameters into Z-parameters, by using expressions (), () and (3), the impedance frequency responses of the common-gate TIA structure are shown in figure 8, where a bandwidth of, GHz can be noticed. The Z in is derived from expression (6) and (), and is shown in figure 8. The output impedance and the transfer function are shown in 8 and 8(c), respectively. In figure 9, Y-parameters for the modified common-gate are shown, where a bandwidth of GHz was obtained. The transfer function is shown in the figure 9(c). This transfer function is compared between simulated results using EK model and experimental results. In the experimental test, it was used the de-embedding technique 4. Experimental results of the photodiode response are shown in figure, where a bandwidth of, GHz can be noticed. In figure, experimental results of the complete OEIC are presented. The OEIC chip must be seeing in the figure 7. A 3 single power supply, and bias currents of 8 ma were used.

4 Ingeniería Electrónica, Automática y Comunicaciones, /5 Figure 7 Microphotography of the modified common-gate TIA Chip. 5 4 Figura 4 Smith-Chart of impedance based in S-parameters. Common-gate TIA and Modified common-gate TIA. 9 5 Z ,$ÃFRPPRQÃDWH 6LPXODWLRQÃ5HDOÃÉÃLPDLQDU\ ([SHULPHQWDOÃ'DWDÃ5HDOÃÉÃLPDLQDU\ Gain (db) 4 3 7,$ÃWUXFWXUH &RPPRQÃDWH Ã6LPXODWLRQÃZLWKÃ& 6 ÃÉÃ& / ÃI G% Ã+] Ã/D\RXWÃZLWKÃ& 6 ÃÉÃ& / ÃI GE Ã+] Ã/D\RXWÃZLWKRXWÃ& 6 ÃÉÃ& / ÃI G% Ã*+] Ã([SHULPHQWDOÃGDWDÃI G% Ã*+] E8 Figure 5 Magnitude response experimental and simulation results of the common-gate TIA. E9 &KLS Z -5 E7 E8 E9 E ,$ÃFRPPRQÃDWH 6LPXODWLRQÃ5HDOÃÉÃLPDLQDU\ ([SHULPHQWDOÃ'DWDÃ5HDOÃÉÃLPDLQDU\ -5 E8 E9 E (c) 4 3 Z ,$ÃFRPPRQÃDWH 6LPXODWLRQÃ5HDOÃÉÃLPDLQDU\ ([SHULPHQWDOÃGDWDÃ5HDOÃÉÃLPDLQDU\ Figure 6 Microphotography of the common-gate TIA prototype. -4 E7 E8 E9 E Figure 8 Experimental and simulation results Z-parameters common-gate TIA. Representation graphs of the Z in Z out and (c) transimpedance, Z v o /i s. 6

5 Two MOS Transimpedance... Y m 5m m 5m -5m 7,$ÃFRPSXHUWDÃFRPXQ FRQÃUHWURDOLPHQWDFLyQÃQHDWLYD Simulación layout -m Imaginaria -5m Experimental Imaginaria -m E7 E8 E9 E Frecuencia (Hz) R d (Ohms) /I f (A - ) p p Y m 8m 6m 4m m -m -4m 7,$ÃFRPPRQÃDWH -6m ZLWKÃQHDWLYHÃIHHGEDFNÃQHWZRUN 6LPXODWLRQ -8m -m Imaginary ([SHULPHQWDO -m Imaginary -4m E7 E8 E9 E Capacitancia (F) 8p 6p 4p p oltaje () Figure Experimental data of the proposed photodiode fabricated. Rd and C obtained of characteristic representation I Gain (db) 3 7,$ÃFRPPRQDWH ZLWKÃQHDWLYH IHHGEDFNÃQHWZRUN Simulation sin C in, out, I -3dB.9 GHz Simulation con C in, out pf, I -3dB.8 GHz Experimental con C in, out pf, I -3dB.8 GHz E7 E8 E9 E (c) Figure 9 Experimental and simulation results Y-parameters modified common-gate TIA. Figure Experimental results of the complete OEIC. 7

6 Ingeniería Electrónica, Automática y Comunicaciones, /5 CONCLUSIONS Two MOS TIA structures, with an integrated photodiode, have been designed and fabricated using a,8 µm BiCMOS AMS process. Experimental results have shown a high transimpedance gain and extended bandwidth performance, with a low power consumption. Measured TIA structures do not present peaking effects, mainly due in other reported works 9 to Miller effect of R f and c gd, and it can be assumed that parasitic effects have been eliminated from the transistor performance. A comparison between simulated and experimental results has shown a reasonable performance of the BSIM3v3 model up to,5 GHz operation. Nevertheless, by using the modified BSIM3v3 model, a better approximation to the fabricated circuit behavior was achieved. But, in the same way, for EK model has a better approximation that the modified BSIM3v3 model. Reason why it is not necessary realized the modified BSIM3v3 model. REFERENCES. SAO,. & B. RAZAI: High-Speed CMOS Circuits for Optical Receivers, Kluwer Academic Publishers,.. OU,. et al.: "CMOS RF Modeling for GHz Communication IC's," LSI Symp. On Tech., Dig. of Tech. Papers, une NG, T. C. et al.: "An Accurate DC to RF Small Signal Model for Deep Submicron MOSFETs Applicable to Multiple Biasing Conditions," Proceedings of ICDA. 4. HALKIAS, G., et al.: ",7 Ghz Bipolar Optoelectronic Receiver Using Conventional,8 µm BiCMOS Process," IEEE ISCAS, May. 5. WU, C. Q.; E. A. SOERO & B. MASSEY: "4-GHz Transimpedance Amplifier with Differential Outputs Using InP- InGaAs Heterojuntion Bipolar Transistors," IEEE. Solid- State Circuits, ol. 38, No. 9, September WEINER,. S. et al.: "SiGe Differential Transimpedance Amplifier With 5-GHz Bandwidth," IEEE. Solid-State Circuits, ol. 38, No. 9, September YAHYA, C. B.: "Design of Wideband Low Noise Transimpedance Amplifiers for Optical Communications," Proc. 43 rd IEEE Midwest Symp. On Circuits and Systems, August. 8. PARK, S. M. & C. TOUMAZOU: "Low Noise Current-Mode CMOS Transimpedance Amplifier for Giga-Bit Optical Communication," IEEE ISCAS, MARTÍNEZ-CASTILLO,. & A. DÍAZ-SÁNCHEZ: "Differential Transimpedance Amplifiers For Communications Systems Based on Common-Gate Topology," IEEE ISCAS, May.. ZIMMERMANN, H.: Integrated Silicon Optoelectronics. Springer-erlag Berlin Heidelberg, New York,.. BUCHER, M. & W. GRABINSKI: "EK MOS Transistor Modelling & RF Application," HP-RF MOS Modelling Workshop, Munich, February 999. AUTHORS aime Martínez Castillo Ingeniero en Instrumentación Electrónica, Doctor en Ciencias en Electrónica, Investigador. Diseño, simulación, modelado, realización de layouts, caraterización y medición de pruebas experimentales de circuitos integrados en sistemas de comunicaciones analógicos para RF y fibra óptica en aplicaciones para altas frecuencias utilizando tecnología MOS. Correo electrónico: jaimemc@aix.ver.ucc.mx Alejandro Díaz Sánchez Ingeniero Electricista, Doctor en Ingeniería Eléctrica. Investigador del INAOE. Diseño de circuitos integrados en modo mixto, procesamiento analógico y digital de señales, arquitecturas de alta eficiencia. Correo electrónico: adiazsan@inaoep.mx Alfonso Torres ácome Ingeniero Químico, Doctor en Ciencias en Electrónica. Investigador del INAOE. Física y tecnología de fabricación de dispositivos y circuitos integrados, optoelectrónica en base de silicio. Correo electrónico: atorres@inaoep.mx Roberto S. Murphy Ingeniero Electrónico, Doctor en Ciencias en Electrónica. Investigador del INAOE. Caracterización, modelado y simulación de dispositivos semiconductores y circuitos integrados, diseño y análisis de antenas para diversas aplicaciones, especialmente en el rango de alta frecuencia y con interés en aplicaciones en circuitos integrados. Correo electrónico: rmurphy@inaoep.mx esús L. Finol Ingeniero Electrónico, Doctor en Ciencias en Electrónica. Científico del Sector Semiconductores para Latinoamérica. Diseño, simulación, modelado, caracterización y medición de pruebas experimentales de circuitos integrados para sistemas de comunicaciones analógo/digitales para RF. Correo electrónico:.finol@motorola.com ol. XXI, No. -3, 5 8