IJVM Instructions. Computer Architecture The instruction opcode is 8 bit wide. Offsets are 16 bits wide (stored in two consecutive bytes)

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(1) IJVM Instructions The instruction opcode is 8 bit wide Offsets are 16 bits wide (stored in two consecutive bytes) For IINC varnum and const are each 8

1 (1) IJVM Instructions The instruction opcode is 8 bit wide Offsets are 16 bits wide (stored in two consecutive bytes) For IINC varnum and const are each 8 bits wide (cannot use WIDE) Variable references are 8 bit wide (or 2 * 8 bits if the instruction is prefixed with WIDE) Constant references are 2 byte wide

2 (2) Main1 fetch PC=PC+1; fetch; goto(mbr) B+1 100

3 (3) NOP goto Main1 Main1

4 (4) IADD 1 read MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR + H; wr; goto Main1 B-1 iadd2

5 (5) IADD 2 MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR + H; wr; goto Main1 B iadd3

6 (6) IADD 3 write MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR + H; wr; goto Main1 A+B Main1

7 (7) ISUB 1 read MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR H; wr; goto Main1 B-1 isub2

8 (8) ISUB 2 MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR H; wr; goto Main1 B isub3

9 (9) ISUB 3 write MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR H; wr; goto Main1 B-A Main1

10 (10) IAND 1 read MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR AND H; wr; goto Main1 B-1 iand2

11 (11) IAND 2 MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR AND H; wr; goto Main1 B iand3

12 (12) IAND 3 write MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR AND H; wr; goto Main1 A andb Main1

13 (13) IOR 1 read MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR OR H; wr; goto Main1 B-1 ior2

14 (14) IOR 2 MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR OR H; wr; goto Main1 B ior3

15 (15) IOR 3 write MAR= SP = SP 1; rd H = TOS MDR = TOS = MDR OR H; wr; goto Main1 A orb Main1

16 (16) DUP 1 fetch MAR = SP = SP + 1 MDR = TOS; wr; goto Main1 B+1 dup2

17 (17) DUP 2 write MAR = SP = SP + 1 MDR = TOS; wr; goto Main1 B Main1

18 (18) POP 1 read MAR = SP = SP 1; rd TOS = MDR; goto Main1 B-1 pop2

19 (19) POP 2 MAR = SP = SP 1; rd TOS = MDR; goto Main1 0 pop3

20 (20) POP 3 MAR = SP = SP 1; rd TOS = MDR; goto Main1 B Main1

21 (21) ILOAD 1 H = LV MAR = MBRU + H; rd MAR = SP = SP + 1 PC = PC + 1; fetch; write; TOS = MDR; goto Main1 B iload2

22 (22) ILOAD 2 read H = LV MAR = MBRU + H; rd MAR = SP = SP + 1 PC = PC + 1; fetch; write; TOS = MDR; goto Main1 A+B iload3

23 (23) ILOAD 3 H = LV MAR = MBRU + H; rd MAR = SP = SP + 1 PC = PC + 1; fetch; write; TOS = MDR; goto Main1 B+1 iload4

24 (24) ILOAD 4 fetch, write H = LV MAR = MBRU + H; rd MAR = SP = SP + 1 PC = PC + 1; fetch; write; TOS = MDR; goto Main1 B+1 iload5

25 (25) ILOAD 5 H = LV MAR = MBRU + H; rd MAR = SP = SP + 1 PC = PC + 1; fetch; write; TOS = MDR; goto Main1 B+1 Main1

26 (26) GOTO 1 OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 MBR= GOTO PC GOTO OFFSET 1OFFSET 2 B-1 goto2

27 (27) GOTO 2 fetch OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 MBR= OFFSET 1 PC GOTO OFFSET 1OFFSET 2 B+1 goto3

28 (28) GOTO 3 fetch OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 H= OFFSET MBR= 0 OFFSET 1 PC GOTO OFFSET 1OFFSET 2 B << 8 goto4

29 (29) GOTO 4 OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 H= OFFSET 1 OFFSET 2 MBR= OFFSET 2 PC GOTO OFFSET 1OFFSET 2 A orb goto5

30 (30) GOTO 5 fetch OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 H= OFFSET 1 OFFSET 2 MBR= OFFSET 2 PC GOTO OFFSET 1OFFSET 2... addr(goto)+ OFFSET A+B goto6

31 (31) GOTO 6 OPC = PC 1 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H PC = OPC + H; fetch goto Main1 Main1

32 (32) IFEQ 1 read MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F B-1 ifeq2

33 (33) IFEQ 2 MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F B ifeq3

34 (34) IFEQ 3 MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F B ifeq4

35 (35) IFEQ 4 HighBit = JAMZ AND Z MAR = SP = SP 1; read OPC = TOS TOS = MDR Z = OPC; IF (Z) GOTO T; ELSE GOTO F If F starts at microaddress 0x092 then T starts at microaddress 0x192 (HighBit = 1) The HighBit is set depending on the value of Z =1 B 0/1 F 001 The value traversing the ALU sets Z

36 (36) T OPC = PC 1; goto goto2; In OPC the address of the conditional test (IFEQ, IF_ICMPEQ,...) is saved Continue as with GOTO, to determine the target jump offset B-1 goto2

37 (37) F 1 PC = PC + 1 PC = PC + 1; fetch goto Main1 B+1 F2

38 (38) F 2 fetch PC = PC + 1 PC = PC + 1; fetch goto Main1 B+1 F3

39 (39) F 3 PC = PC + 1 PC = PC + 1; fetch goto Main1 Main1

40 (40) WIDE fetch PC=PC+1;fetch; goto(mbr or 0x100) As variables are referenced with their offset from the LV pointer, to access variables stored at an offset bigger than 256 bytes the WIDE prefix is to be called before the ILOAD or ISTORE instruction (which normally take 8 bit offsets). WIDE make possible to use 16 bit offsets in the following instruction. MBR contains the opcode of the next instruction (ILOAD or ISTORE). The wide version of ILOAD and ISTORE are located at: WIDE_ILOAD is at (addr of ILOAD) OR 0x100 WIDE_ISTORE is at (addr of ISTORE) OR 0x100 B+1 0x

41 (41) WIDE_ISTORE 1 fetch PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H MAR = LV + H; goto istore3 B+1 wide_istore2

42 (42) WIDE_ISTORE 2 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H MAR = LV + H; goto istore3 B << 8 wide_istore3

43 (43) WIDE_ISTORE 3 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H MAR = LV + H; goto istore3 A orb wide_istore4

44 (44) WIDE_ISTORE 4 PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H MAR = LV + H; goto istore3 A+B istore3

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