Flip-flops Luis Entrena, Celia López, Mario García, Enrique San Millán Universidad Carlos III de Madrid 1
igital circuits and microprocessors Inputs Output Functions Outputs State Functions State Microprocessor ALU Combinational Sequential Registers RAM ROM Control Peripherals Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 2
Outline l Introduction The flip-flop as the basic memory element Flip-flop classification l Asynchronous flip-flops l Synchronous flip-flops l Synchronous flip-flops with asynchronous inputs l Flip-flop control logic l Timing characteristics l Synchronous circuits l Circuits with flip-flops: chronograms Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 3
1. Introductión: flip-flops l l efinition: Circuit storing an information bit. It has two stable states, logic 0 and logic 1. The state does not change until the control inputs allow it. Classification Control logic: inputs determining the new state, T, SR, JK Syncronism: Asynchronous: can change the state in response to any input, at any time Synchronous: they have a control input that states when the state can change Level-triggered Edge-triggered Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 4
2. Asynchronous flip-flop l SR asynchronous flip-flop S= 1 => Set R= 1 => Reset S=R= 0 => Keep state l Characteristics Memory: it keeps the state if inputs are not active Asynchronous: the state changes inmediately if R or S are activated 0 1 0 1 On Off S R Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 5
Asynchronous flip-flop l State keeping circuit 1 0 1 0 1 0 Two stable states l With control signals R S R / 0 0 / Keep state 1 0 1 0 Set S / 0 1 1 1 0 1 0 0 Reset Forbidden state Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 6
3. Level-triggered synchronous flip-flop l It has a control signal that allows the state to be changed l Level-triggered synchonous Flip-flop (-latch) C= 1 => state changes to value C= 0 => keep state C / C 0 1 / C 0 X 1 0 1 1 / / 0 1 1 0 Keep state Assign 0 Assign 1 Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 7
Edge-triggered synchronous flipflop l Edge-triggered synchonous flip-flop LATCH Edge detector / Clk C / Edge detector tp,inv Clk C Clk /Clk Bad solution due to technology. Inverter delay is not controllable. C Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 8
Master-Slave synchronous flipflop l Two latches active with opposite levels MASTER M SLAVE E = C C Clk Master Slave Master Slave Clk M E l l E changes only in clock rising edges E new value is value just before the clock edge Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 9
Edge triggered synchonous flipflop l l l l The one used most Only changes in clock edges (normally rising edges) The output change takes place just before the edge The output new value is taken from input just before the edge Clk Clk Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 10
4. Synchronous flip-flops with asynchronous inputs l Synchronous flip-flops with asynchronous inputs for initialization Clear: asynchronous initialitation to 0 Preset: asynchronous initialitation to 1 Usually low-level active preset / preset clear clear Clk Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 11
5. Flip-flop control logic l Flip-flop inputs control the way the state is changed Kinds of flip-flops depending on the inputs:,t,jk,sr Enable signal: Allows/prevents the state to change In nof enabled, the state is kept Synchronous initialization Set to 0 ir 1 in a synchronous way Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 12
Flip-flop control logic l Working tables escribe functionality flip-flop (ata) 0 1 0 1 T flip-flop (Toggle) T 0 1 / SR flip-flop (Set-Reset) S R 0 0 0 1 1 0 0 1 JK flip-flop (Jump & Kill) J K 0 0 0 1 1 0 1 1 0 1 / l Transition tables escribes the new state in terms of the present state and input values flip-flop 0 0 0 0 1 0 1 0 1 1 1 1 T flip-flop T 0 0 0 0 1 1 1 0 1 1 1 0 Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 13
Flip-flop control logic l Flip-flops with enable E / flip-flop E 0 X 1 0 0 T flip-flop E 0 X 1 0 T E / 1 1 1 1 1 / E 0 1 / T E T / Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 14
Flip-flop control logic l Flip-flop with synchronous initialization Set: forces 1 Reset: forces 0 l Example: flip-flop with Enable, Set and Reset Priority: Reset, Set, Enable E /S /R E /S 0 1 / /R Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 15
6. Timing characteristics l Timing flip-flop restrictions Clock level length (t 0min,t 1min ) Asynchronous signals length (t reset min ) ata insertion times (t setup,t hold ) clear clk (t reset mín ) (t setup,t hold ) (t omín,t 1mín ) Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 16
7. Synchronous circuits l Synchronous circuit Every flip-flop use the same clock Every flip-flop is triggered by the same clock edge (usually the rising edge) There is a common initialization signal called Reset / / / Clk Reset Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 17
Synchronous circuits: the clock cycle l Critical path: Path between two flip-flops with the larger delay Slowest path between two flip-flops. It determines the maximum allowable clock frequency for the circuit. Clk t Clk t Clk > t hold + t crítico + t setup t hold t crítico t setup f Clk = 1 / t Clk t Clk = 1ns f Clk = 1GHz Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 18
7. Chronograms l Edge detector Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 19
Chronograms l Counter Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 20
Bibliography l Circuitos y Sistemas igitales. J. E. García Sánchez,. G. Tomás, M. Martínez Iniesta. Ed. Tebar-Flores l Electrónica igital, L. Cuesta, E. Gil, F. Remiro, McGraw-Hill l Fundamentos de Sistemas igitales, T.L Floyd, Prentice-Hall Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid, 2008 21